The use of RTL descriptions in accurate timing verification and test generation (VLSI)

Roy K.

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The use of RTL descriptions in accurate timing verification and test generation (VLSI)

机译：在准确的时序验证和测试生成（VLSI）中使用RTL描述

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The authors discuss the use of high-level information in two major problems of VLSI system design: (1) accurate timing verification to eliminate false paths due to reconvergent fan-out, redundancy, and control signal constraints, and (2) testing for stuck-at-faults. The register-transfer-level (RTL) descriptions provide the set of control signals for valid data operations. Using this set of control signals, the timing verifier can perform an efficient estimation of critical path delays for only valid data transfers. This approach to critical path justification can be extended to test generation for a class of sequential circuits where all latches and memory elements can be explicitly identified. Test generation for complex VLSI circuits composed of many interconnected modules is discussed. Sequential propagation and justification of signals are carried out using the data flow information. Results based on an implementation of the algorithms are presented.

机译：作者讨论了在VLSI系统设计的两个主要问题中使用高级信息：（1）准确的时序验证，以消除由于重新收敛的扇出，冗余和控制信号约束而导致的错误路径，以及（2）测试卡住情况断断续续。寄存器传输级别（RTL）描述为有效的数据操作提供了一组控制信号。使用这组控制信号，时序验证器可以仅对有效数据传输执行关键路径延迟的有效估计。可以将这种用于关键路径调整的方法扩展为测试一类时序电路的生成，在该时序电路中可以明确标识所有锁存器和存储元件。讨论了由许多互连模块组成的复杂VLSI电路的测试生成。使用数据流信息进行信号的顺序传播和证明。给出了基于算法实现的结果。

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《IEEE Journal of Solid-State Circuits》 |1991年第9期|P.1230-1239|共10页
作者
Roy K.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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机译：基于动态统计时间分析的VLSI路径延迟测试模式生成
2. Formal Probabilistic Timing Verification in RTL [J] . Kumar J.A., Vasudevan S. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2013,第5期

机译：RTL中的正式概率时序验证
3. Accurate area and delay estimation from RTL descriptions [J] . Srinivasan A., Huber G.D. IEEE transactions on very large scale integration (VLSI) systems . 1998,第1期

机译：根据RTL描述进行准确的面积和延迟估计
4. A Novel Approach to Accurate Timing Verification Using RTL Descriptions [C] . Roy K., Abraham J.A. World Class Manufacture for SMEs: Some ot the Issues . 1996

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The use of RTL descriptions in accurate timing verification and test generation (VLSI)

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