A 150-MHz direct digital frequency synthesizer in 1.25- mu m CMOS with -90-dBc spurious performance

Nicholas H.T. III; Samueli H.

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A 150-MHz direct digital frequency synthesizer in 1.25- mu m CMOS with -90-dBc spurious performance

机译：具有1.25μmCMOS的150MHz直接数字频率合成器，具有-90dBc的杂散性能

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A monolithic CMOS direct digital frequency synthesizer (DDFS) is presented which simultaneously achieves high spectral purity and wide bandwidth. Phase noise of the output sine wave is equivalent to or better than that of the 150-MHz reference clock. The synthesizer covers a bandwidth from DC to 75 MHz in steps of 0.035 Hz with a switching speed of 6.7 ns and a tuning latency of 13 clock cycles. An efficient look-up table method for calculating the sine function reduces ROM storage requirements by a factor of 128:1. All circuit designs are fully static and are tolerant to transistor threshold shifts caused by radiation or process variations. The DDFS was fabricated in a 1.25- mu m radiation-hardened double-level metal bulk P-well CMOS process which is tolerant to over 10/sup 6/ rd(Si) of total dose radiation. The die size is 195 mil*195 mil with a device count of 35,000 transistors. Power dissipation is 950 mW at a clock rate of 100 MHz.

机译：提出了一种单片CMOS直接数字频率合成器（DDFS），它可以同时实现高频谱纯度和宽带宽。输出正弦波的相位噪声等于或优于150 MHz参考时钟的相位噪声。该合成器以0.035 Hz的步长覆盖DC到75 MHz的带宽，开关速度为6.7 ns，调谐延迟为13个时钟周期。用于计算正弦函数的高效查找表方法将ROM存储需求降低了128：1。所有电路设计都是完全静态的，并且可以承受由辐射或工艺变化引起的晶体管阈值漂移。 DDFS是在1.25微米的辐射硬化双层金属体P阱CMOS工艺中制造的，该工艺可耐受总剂量辐射的10 / sup 6 / rd（Si）以上。芯片尺寸为1.95亿* 1.95亿，器件数量为35,000个晶体管。时钟频率为100 MHz时，功耗为950 mW。

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来源
《IEEE Journal of Solid-State Circuits》 |1991年第12期|P.1959-1969|共11页
作者
Nicholas H.T. III; Samueli H.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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A 150-MHz direct digital frequency synthesizer in 1.25- mu m CMOS with -90-dBc spurious performance

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