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首页> 外文期刊>IEEE Journal of Solid-State Circuits >An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller
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An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller

机译:具有片上擦除/擦除验证控制器的80ns 1Mb闪存

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摘要

An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 mu /sup 2/. The die area is 32.3 mm/sup 2/. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.
机译:内部擦除和擦除验证控制系统已在可电擦除,可重新编程的80 ns 1-Mb闪存中实现,适用于系统内重新编程应用。该存储器利用一个单元面积为10.4μs/ sup 2 /的单晶体管型单元。模具面积为32.3mm / sup 2 /。擦除模式由50 ns的脉冲启动。擦除和擦除验证序列在芯片中自动进行,无需任何其他外部控制。可以通过状态轮询模式检查内部状态。 80 ns的访问时间是由先进的读出放大器以及低电阻的多晶硅字线和成比例的外围晶体管引起的。为了实现高灵敏度,高速感测电路,将pMOS晶体管(其栅极连接至其漏极)用作负载晶体管。

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