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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 0.23- μg Bias Instability and 1- μg/√ Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL
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A 0.23- μg Bias Instability and 1- μg/√ Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL

机译:具有PLL的嵌入式频率数字转换器的0.23μg偏置不稳定性和1μg/√Hz加速度噪声密度硅振荡加速度计

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This paper presents a silicon oscillating accelerometer (SOA) with a new CMOS readout circuit architecture. A phase lock loop (PLL) with a hybrid and antinoise folding PFD is employed to sustain the oscillation of the MEMS oscillator, and the oscillation amplitude is set by an external reference. In addition, a sigma-delta frequency-to-digital converter is combined with the PLL to digitize the accelerometer's frequency output for low power consumption. The MEMS transducer and the readout circuit are fabricated in an 80-μm SOI and standard 0.35-μm CMOS process, respectively. The SOA achieves 0.23-μg bias instability and 1-μg/Hz1/2 acceleration noise density with a ±30 g full-scale, which are equivalent to 4-ppb relative instability and 17-ppb/Hz1/2 relative acceleration noise density. It only consumes 2.7 mW under a 1.5 V supply.
机译:本文提出了一种具有新型CMOS读出电路架构的硅振荡加速度计(SOA)。采用具有混合和抗噪折叠PFD的锁相环(PLL)来维持MEMS振荡器的振荡,并且振荡幅度由外部基准设定。此外,一个sigma-delta频率数字转换器与PLL结合使用,可将加速度计的频率输出数字化,从而降低了功耗。 MEMS换能器和读出电路分别以80μmSOI和标准0.35μmCMOS工艺制造。 SOA达到0.23μg偏置不稳定性和1-μg/ Hz1 / 2的加速度噪声密度,满量程为±30 g,这相当于4 ppb的相对不稳定性和17 ppb / Hz1 / 2的相对加速度的噪声密度。在1.5 V电源下,其功耗仅为2.7 mW。

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