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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Multigate-Cell Stacked FET Design for Millimeter-Wave CMOS Power Amplifiers
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Multigate-Cell Stacked FET Design for Millimeter-Wave CMOS Power Amplifiers

机译:用于毫米波CMOS功率放大器的多栅极单元堆叠FET设计

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To increase the voltage handling capability of scaled CMOS-based circuits, series connection (stacking) of transistors has been demonstrated in recently reported mm-wave power amplifiers. This paper discusses the implementation of stacked CMOS circuits employing a compact, multigate layout technique, rather than the conventional series connection of individual transistors. A unit multigate FET is composed of a single transistor with one source and drain and multiple (four) gate connections. Capacitances are implemented in a distributed manner allowing close proximity to the individual gate fingers using metal layers available within the CMOS back-end-of-line (BEOL) stack. The multigate structure is demonstrated to decrease parasitic resistances and capacitances, and has better layout for heat-sinking. The unit cell is replicated through tiling to implement larger effective gate widths. Millimeter-wave power amplifiers using the multigate-cell are presented which operate over the 25-35 GHz band and achieve 300 mW of saturated output power and peak power-added efficiency (PAE) of 30% in 45 nm CMOS SOI technology. To the authors' knowledge, the output power is the best reported for a single stage CMOS power amplifier that does not use power-combining for this frequency range.
机译:为了提高按比例缩放的基于CMOS的电路的电压处理能力,在最近报道的毫米波功率放大器中已经证明了晶体管的串联连接(堆叠)。本文讨论了采用紧凑的多栅极布局技术而不是单个晶体管的常规串联方式来实现堆叠CMOS电路的方法。单元多栅极FET由具有一个源极和漏极以及多个(四个)栅极连接的单个晶体管组成。电容以分布式方式实现,允许使用CMOS后端(BEOL)堆栈中可用的金属层紧密靠近各个栅极指。事实证明,多栅极结构可降低寄生电阻和电容,并具有更好的散热布局。通过平铺复制单位单元,以实现更大的有效栅极宽度。提出了使用多栅极单元的毫米波功率放大器,该放大器在25-35 GHz频带上工作,并在45 nm CMOS SOI技术中达到300 mW的饱和输出功率和30%的峰值功率附加效率(PAE)。据作者所知,对于在该频率范围内不使用功率组合的单级CMOS功率放大器,输出功率是报告得最好的。

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