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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
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A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

机译：基于65 nm CMOS的两级环形振荡器的40 Gb / s串行链路发送器的7.6 mW，414 fs RMS抖动10 GHz锁相环

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摘要

This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverter-based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB.
机译：本文介绍了用于40 Gb / s串行链路发送器（TX）的10 GHz锁相环（PLL）的设计。两级环形振荡器用于为四分之一速率的TX提供四相，10 GHz时钟。本文讨论了几种分析和验证技术，从用于40 Gb / s TX的时钟架构到两级环形振荡器的振荡故障，不一而足。基于三态逆变器的分频器和一个交流耦合的时钟缓冲器被用于以最小的功率和面积开销进行高速操作。拟议中的采用65 nm CMOS技术制造的10 GHz PLL占据了0.009平方毫米的有效面积，从10 kHz到100 MHz的积分RMS抖动为414 fs，而1.2 V电源的功耗为7.6 mW。产生的品质因数为-238.8 dB，比最新的环形PLL高4 dB。

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  • 来源
    《IEEE Journal of Solid-State Circuits》 |2016年第10期|2357-2367|共11页
  • 作者

    Woorham Bae; Haram Ju; Kwanseo Park; Sung-Yong Cho; Deog-Kyoon Jeong;

  • 作者单位

    Department of Electrical and Computer Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea;

    Department of Electrical and Computer Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea;

    Department of Electrical and Computer Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea;

    Department of Electrical and Computer Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea;

    Department of Electrical and Computer Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Ring oscillators; CMOS integrated circuits; Clocks; Phase locked loops; Inverters; CMOS technology; Bandwidth;

    机译：环形振荡器;CMOS集成电路;时钟;锁相环;逆变器;CMOS技术;带宽;

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