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首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A 0.4 V 63 src='/images/tex/241.gif' alt='mu'> W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator
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A 0.4 V 63 src='/images/tex/241.gif' alt='mu'> W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator

机译:使用混合动力的0.4 V 63 src =“ / images / tex / 241.gif” alt =“ mu”> W 76.1 dB SNDR 20 kHz带宽Delta-Sigma调制器开关积分器

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This paper presents a delta-sigma modulator operating at a supply voltage of 0.4 V. The designed delta-sigma modulator uses a proposed hybrid switching integrator and operates at a low supply voltage without clock boosting or bootstrapped switches. The proposed integrator consists of both switched-resistor and switched-capacitor operations and significantly reduces distortion at a low supply voltage. Variation in the turn-on resistance, which is the main source of distortion, is avoided by placing the switches at the virtual ground node of the amplifier. The proposed low-voltage design scheme can replace commonly-used clock boosting techniques, which rely on internal high-voltage generation circuits. A fabricated modulator achieves a 76.1 dB signal-to-noise-plus-distortion ratio (SNDR) and an 82 dB dynamic range at a 20 kHz bandwidth. The measured total power consumption is 63 µW from a 0.4 V supply voltage. The measured results show robust SNDR performance, even at ±10% supply voltage variations. The measured results also show stable performance over a wide temperature range.
机译:本文介绍了一种在0.4 V的电源电压下工作的delta-sigma调制器。设计的delta-sigma调制器使用一种建议的混合开关积分器,并在低电源电压下工作,而没有时钟提升或自举开关。拟议的积分器包括开关电阻和开关电容器两种操作,可显着降低低电源电压下的失真。通过将开关放置在放大器的虚拟接地节点上,可以避免导通电阻的变化,这是失真的主要来源。所提出的低压设计方案可以代替依靠内部高压产生电路的常用时钟升压技术。预制调制器在20 kHz带宽下可实现76.1 dB的信噪加失真比(SNDR)和82 dB的动态范围。从0.4 V电源电压测得的总功耗为63 µW。测量结果表明,即使在±10%的电源电压变化下,SNDR性能也很稳定。测量结果还显示出在宽温度范围内的稳定性能。

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