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首页> 外文期刊>IEEE Journal of Solid-State Circuits >InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR
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InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR

机译:基于InP HBT / Si CMOS的13-b 1.33-Gsps数模转换器,SFDR大于70dB

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摘要

A prototype 13-b 1.33-Gsps digital-to-analog converter (DAC) implemented in a unique heterogeneous integration process (combining 0.45-µm InP HBT with 0.18-µm CMOS) is presented. Measured performance of greater than 70 dB SFDR is achieved across a 500-MHz bandwidth centered at 1 GHz (second Nyquist band). Heterogeneous integration enables each circuit element to be implemented in the transistor technology best suited to the circuit function. Low dc power is achieved by implementing the digital front-end in a standard silicon CMOS technology, while InP HBT technology is used to implement the high-speed/high-precision current-steering DAC core. The core DAC employs a segmented architecture with three unary most significant bits and an R-2R ladder for the ten least significant bits. No calibration circuitry is required to achieve better than 11 b of dc linearity. Dynamic performance is enhanced by employing an ultra-high-linearity return-to-zero (RZ) analog output deglitcher switch. Measured performance data for three different circuit design variations of the output switch (incorporating a varying mix of CMOS and InP HBT devices) is presented.
机译:展示了一种原型13-b 1.33-Gsps数模转换器(DAC),该转换器以独特的异构集成工艺(将0.45-µm InP HBT与0.18-µm CMOS结合使用)实现。在以1 GHz(第二奈奎斯特频带)为中心的500 MHz带宽上,可实现超过70 dB SFDR的测量性能。异构集成使每个电路元件都能以最适合电路功能的晶体管技术实现。通过在标准硅CMOS技术中实现数字前端可实现低dc功耗,而InP HBT技术则用于实现高速/高精度电流控制DAC内核。核心DAC采用分段架构,具有三个一元最高有效位,以及一个R-2R阶梯用于十个最低有效位。无需任何校准电路即可获得优于11 b的直流线性度。通过采用超高线性归零(RZ)模拟输出去毛刺开关,可以提高动态性能。给出了输出开关的三种不同电路设计变化(包括CMOS和InP HBT器件的变化混合)的测量性能数据。

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