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首页> 外文期刊>IEEE Journal of Solid-State Circuits >High dynamic range InP HBT delta-sigma analog-to-digital converters
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High dynamic range InP HBT delta-sigma analog-to-digital converters

机译：高动态范围InP HBTΔ-Σ模数转换器

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摘要

To date, the development of multifunction multicarrier digital receivers for cellular base station and military communications applications has been limited by the demanding dynamic range requirements for the analog-to-digital converter (ADC). The use of oversampling delta-sigma modulators provides a promising approach to overcoming the dynamic range barriers Nyquist-rate converters face in the same applications. This paper discusses issues involved in the design of high-speed high dynamic range wide-band delta-sigma ADCs for such communications applications. Test results of prototype designs are also presented. The delta-sigma modulators described in this paper operate at sampling frequencies ranging from 1 to 2.5 GHz with center frequencies ranging from dc to 100 MHz, providing between 74 and 84.2 dB signal-to-noise ratio (12 and 13.7 bits) for bandwidths of 25 and 12.5 MHz, respectively. The loop filters are continuous-time low-pass and bandpass implementations of order 6 and 10, and were fabricated in an InP heterojunction bipolar (HBT) technology. A typical tenth-order design consumes 6 W of power and occupies a die area of 23.5 mm2.
机译：迄今为止，用于蜂窝基站和军事通信应用的多功能多载波数字接收机的发展受到对模数转换器（ADC）的动态范围要求的限制。过采样Δ-Σ调制器的使用提供了一种有前途的方法，可以克服奈奎斯特速率转换器在相同应用中面临的动态范围障碍。本文讨论了用于此类通信应用的高速高动态范围宽带delta-sigma ADC设计中涉及的问题。还介绍了原型设计的测试结果。本文所述的delta-sigma调制器在1至2.5 GHz的采样频率下工作，而中心频率在dc至100 MHz的范围内工作，提供了74至84.2 dB的信噪比（12至13.7位），带宽为。 25和12.5 MHz。环路滤波器是6阶和10阶的连续时间低通和带通实现，并采用InP异质结双极（HBT）技术制造。典型的十阶设计消耗6 W的功率，并占用23.5 mm2的芯片面积。

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