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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications
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A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications

机译：适用于10G以太网应用的10.3GS / s，6位Flash ADC

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摘要

This paper presents the design of a 40-nm CMOS 10.3-GS/s 6-bit Flash ADC used as the analog frontend of a universal DSP-based receiver that meets the requirements for all the NRZ 10G Ethernet (10GE) standards, for both fiber and copper channels. The 4-way interleaved ADC consists of a pair of frontend variable gain amplifiers (VGAs) driving four sets of track-and-hold (T/H) switches, followed by fine VGAs that drive 6-bit comparator arrays. A Wallace-tree adder is utilized as the thermometer-to-binary encoder allowing comparator re-ordering and redundancy. Also integrated is an 8-bit calibration DAC that is used as a reference to nullify the accumulated offset of the entire signal path, as well as to compensate for the nominal nonlinearity of the fine VGA and the resistor ladder. After calibration, the peak SNDR of the ADC is about 34 dB with bandwidth ranging from 3.5 to 6 GHz over all VGA gain settings. The ADC, along with its entire clock path, occupies 0.27 mm $^{2}$ and consumes 242 mW from a 0.9-V supply.
机译：本文介绍了一种40nm CMOS 10.3-GS / s 6位Flash ADC的设计，该ADC用作基于通用DSP的接收器的模拟前端，该接收器同时满足所有NRZ 10G以太网（10GE）标准的要求。光纤和铜通道。 4路交错式ADC由一对前端可变增益放大器（VGA）组成，它们驱动四组采样保持（T / H）开关，然后是驱动6位比较器阵列的精细VGA。华莱士树加法器用作温度计到二进制的编码器，从而允许比较器重新排序和冗余。还集成了一个8位校准DAC，用作基准，以消除整个信号路径的累积偏移，并补偿精细VGA和梯形电阻的标称非线性。校准后，在所有VGA增益设置上，ADC的峰值SNDR约为34 dB，带宽范围为3.5至6 GHz。 ADC及其整个时钟路径占用0.27 mm 2，在0.9 V电源下的功耗为242 mW。

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