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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth
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A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

机译:具有88-DB动态范围和1.1MHz信号带宽的连续时间Sigma-Delta调制器

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摘要

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.
机译:本文介绍了用于ADSL应用的连续时间/ SPL Sigma // SPL Delta /调制器的设计和实验结果。 MultiBIT Nonreturn-Zero(NRZ)DAC脉冲整形用于减少时钟抖动灵敏度。传统连续时间/ SPL Sigma // SPL Delta /调制器中的非零多循环延迟问题由我们提出的架构解决。用5位内部量化的原型三阶连续时间/ SPL SIGMA // SPLΔ/调制器在0.5 / SPL MU / M双多金属三金属CMOS技术中实现,芯片面积为2.4 / SPL时间/ 2.4 mm / sup 2 /。实验结果表明,该调制器通过超采样比为16.3-MHz信号带宽实现了88-DB动态范围,84 dB SNR和83-DB SNDR,同时从3.3V电源耗散62兆瓦。

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