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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth
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A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

机译:具有88dB动态范围和1.1MHz信号带宽的连续时间sigma-delta调制器

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This paper presents the design and experimental results of a continuous-time ΣΔ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time ΣΔ modulators is solved by our proposed architecture. A prototype third-order continuous-time ΣΔ modulator with 5-bit internal quantization was realized in a 0.5-Μm double-poly triple-metal CMOS technology, with a chip area of 2.4 × 2.4 mm2. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.
机译:本文介绍了用于ADSL应用的连续时间ΣΔ调制器的设计和实验结果。多位不归零(NRZ)DAC脉冲整形用于降低时钟抖动灵敏度。我们提出的架构解决了传统连续时间ΣΔ调制器中的非零过量环路延迟问题。具有0.5位内部量化的原型三阶连续时间ΣΔ调制器是在0.5微米双多晶硅三金属CMOS技术中实现的,芯片面积为2.4×2.4 mm2。实验结果表明,该调制器在1.1MHz信号带宽上具有88dB的动态范围,84dB的SNR和83dB的SNDR,过采样率为16,而从3.3V电源消耗的功率为62mW。

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