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A leakage reduction methodology for distributed MTCMOS

机译：分布式MTCMOS的泄漏方法

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摘要

Multithreshold CMOS (MTCMOS) circuits reduce standby leakage power with low delay overhead. Most MTCMOS designs cut off the power to large blocks of logic using large sleep transistors. Locally distributing sleep devices has remained less popular even though it has several advantages described in this paper. However, locally placed sleep devices are only feasible if sneak leakage currents are prevented. This paper makes two contributions to leakage reduction. First, we examine the causes of sneak leakage paths and propose a design methodology that enables local insertion of sleep devices for sequential and combinational circuits. A set of design rules allows designers to prevent most sneak leakage paths. A fabricated 0.13-Μm, dual VT test chip employs our methodology to implement a low-power FPGA architecture with gate-level sleep FETs and over 8× measured standby current reduction. Second, we describe the implementation and benefits of local sleep regions in our design and examine the interfacing issues for this technique. Local sleep regions reduce leakage in unused circuit components at a local level while the surrounding circuits remain active. Measured results show that local sleep regions reduce leakage in active configurable logic blocks (CLBs) on our chip by up to 2.2× (measured) based on configuration.
机译：多线程CMOS（MTCMOS）电路减少待机漏电功率，低延迟开销。大多数MTCMOS设计使用大型睡眠晶体管切断大量逻辑块。即使在本文中描述了几个优点，本地分配睡眠设备仍然不太受欢迎。然而，如果防止潜水漏电流，则当地放置的睡眠装置仅是可行的。本文对泄漏减少进行了两项贡献。首先，我们检查潜行泄漏路径的原因，并提出了一种设计方法，使局部插入睡眠装置用于顺序和组合电路。一组设计规则允许设计人员防止大多数潜行泄漏路径。使用的0.13-μm，双VT测试芯片采用我们的方法来实现具有门级睡眠FET的低功耗FPGA架构，并以超过8倍测量的待机电流减小。其次，我们描述了我们设计中当地睡眠地区的实施和益处，并检查了这种技术的接口问题。当地睡眠区域在局部级别减少未使用的电路元件的泄漏，而周围电路仍然有效。测量结果表明，本地睡眠区域通过基于配置将芯片上的活动可配置逻辑块（CLB）的泄漏减少到2.2倍（测量）。

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