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A leakage reduction methodology for distributed MTCMOS

机译：分布式MTCMOS的减少泄漏方法

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摘要

Multithreshold CMOS (MTCMOS) circuits reduce standby leakage power with low delay overhead. Most MTCMOS designs cut off the power to large blocks of logic using large sleep transistors. Locally distributing sleep devices has remained less popular even though it has several advantages described in this paper. However, locally placed sleep devices are only feasible if sneak leakage currents are prevented. This paper makes two contributions to leakage reduction. First, we examine the causes of sneak leakage paths and propose a design methodology that enables local insertion of sleep devices for sequential and combinational circuits. A set of design rules allows designers to prevent most sneak leakage paths. A fabricated 0.13-Μm, dual VT test chip employs our methodology to implement a low-power FPGA architecture with gate-level sleep FETs and over 8× measured standby current reduction. Second, we describe the implementation and benefits of local sleep regions in our design and examine the interfacing issues for this technique. Local sleep regions reduce leakage in unused circuit components at a local level while the surrounding circuits remain active. Measured results show that local sleep regions reduce leakage in active configurable logic blocks (CLBs) on our chip by up to 2.2× (measured) based on configuration.
机译：多阈值CMOS（MTCMOS）电路以低延迟开销降低了待机泄漏功率。大多数MTCMOS设计都使用大型睡眠晶体管来切断大型逻辑块的电源。即使本地分布的睡眠设备具有本文所述的几个优点，也仍然不那么受欢迎。但是，只有在防止潜电流泄漏的情况下，本地放置的睡眠设备才可行。本文为减少泄漏做出了两点贡献。首先，我们检查了潜行泄漏路径的原因，并提出了一种设计方法，该方法可以在顺序和组合电路中局部插入睡眠设备。一组设计规则使设计师可以防止大多数潜行泄漏路径。预制的0.13μm，双VT测试芯片采用我们的方法来实现具有门级睡眠FET的低功耗FPGA架构，并测得的待机电流降低了8倍以上。其次，我们在设计中描述了局部睡眠区域的实现方式和优势，并研究了该技术的接口问题。局部休眠区域可在局部水平上减少未使用的电路组件中的泄漏，同时使周围电路保持活动状态。测量结果表明，基于配置，本地睡眠区域将我们芯片上活动的可配置逻辑块（CLB）的泄漏降低了2.2倍（测量值）。

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