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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme
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A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

机译:具有数据总线窗口延长技术的16 GB 640-GB / S HBM2E DRAM和协同末端ECC方案

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摘要

Circuit and design techniques are presented for enhancing the performance and reliability of a 3-D-stacked high bandwidth memory-2 extension (HBM2E). A data-bus window extension technique is implemented to cope with reduced clock cycle time ranging from data-path architecture, through-silicon via (TSV) placement, and TSV-PHY alignment. A power TSV placement in the middle of array and at the chip edge along with a dedicated top metal for power mesh improves power IR drop by 62%. An on-die ECC (OD-ECC) scheme featuring a self-scrubbing function is designed to be orthogonal to system ECC. An uncorrectable bit error rate (UBER) is improved by 10(5) times with the proposed OD-ECC and scrubbing scheme. A memory built-in self-test (MBIST) block supports low-frequency cell and core test in a parallel manner and all channel at-speed operation with adjustable ac parameters. The proposed parallel-bit MBIST reduces test time by 66%. A 16-GB HBM2E fabricated in the second generation of 10-nm class DRAM process achieves a bandwidth up to 640 GB/s (5 Gb/s/pin) and provides a stable bit-cell operation at a high temperature (e.g., 105 degrees C).
机译:提高了电路和设计技术,用于提高3-D堆叠高带宽存储器-2扩展(HBM2E)的性能和可靠性。实现数据总线窗口扩展技术以应对从数据路径架构,硅通孔(TSV)放置和TSV-PHY对准的降低的时钟周期时间。阵列中间的电源TSV放置和芯片边缘以及用于电源网的专用顶部金属的电源IR降至62%。模具ECC(OD-ECC)方案具有自洗涤功能的设计旨在与系统ECC正交。使用所提出的OD-ECC和擦洗方案,将不可识别的比特错误率(优步)提高10(5)次。内置自检(MBist)块以平行方式支持低频单元和核心测试,以及具有可调AC参数的所有通道速度操作。所提出的并行比特MBIST将测试时间降低66%。在第二代10-NM类DRAM过程中制造的16GB HBM2E实现高达640 GB / s(5 GB / S / PIN)的带宽,并在高温下提供稳定的比特单元操作(例如,105 C)。

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