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首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber
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A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

机译：具有数字校准功能的基于ADC的500 mW CMOS AFE，可通过KR背板和多模光纤进行10 Gb / s串行链路

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摘要

This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 $~$Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) and a 6-bit 4-way time-interleaved ADC, which is digitally calibrated to compensate for the offset, gain and phase mismatches between the interleaved channels. With a 5 GHz input signal, the ADC achieves overall SNDR of 29 dB, while the measured SNDR of flash sub-ADC is 31.6 dB. The power efficiency FoM of the complete interleaved ADC is 1.4 pJ per conversion step. The PLL uses a calibrated LC-VCO and the TX features a full-rate 3-tap de-emphasis at the output. Inductively tuned buffers connected in tandem are employed to distribute the 10$~$ GHz clock. Random and deterministic jitter measured at the TX output are 0.38$~{hbox {ps}}_{rm rms}$ and 2.65$~{hbox {ps}}_{rm pp}$, respectively. Implemented in 65 nm CMOS technology, the AFE occupies an area of 3$~{hbox {mm}}^{2}$ and consumes 500 mW from a 1 V supply. BER of less than 10$^{-15}$ is measured over legacy backplanes with 26$~$dB loss at Nyquist and the measured transceiver optical sensitivity is less than $-hbox{13~dBm}$ for all four LRM stressors, exceeding both the KR and the LRM specifications.
机译：本文介绍了集成到基于DSP的收发器中的模拟前端（AFE）的设计，该收发器适用于串行10 $〜$ Gbps KR背板和长距离多模光纤（LRM）应用。接收器由一个可编程增益放大器（PGA）和一个6位4路时间交错ADC组成，该ADC经过数字校准以补偿交错通道之间的偏移，增益和相位失配。对于5 GHz输入信号，ADC的整体SNDR为29 dB，而闪存子ADC的实测SNDR为31.6 dB。完整的交错ADC的功率效率FoM为每个转换步骤1.4 pJ。 PLL使用校准的LC-VCO，而TX在输出端具有全速率3抽头去加重。串联连接的电感调谐缓冲器用于分配10 $〜$ GHz时钟。在TX输出处测得的随机抖动和确定性抖动分别为0.38 $〜{hbox {ps}} _ {rm rms} $和2.65 $〜{hbox {ps}} _ {rm pp} $。 AFE采用65 nm CMOS技术实现，占地3 $〜{hbox {mm}} ^ {2} $，并通过1 V电源消耗500 mW。 BER小于10 $ ^ {-15} $是在传统背板上测得的，在Nyquist处有26 $〜$ dB的损耗，并且对于所有四个LRM压力源，测得的收发器光敏度均小于$ -hbox {13〜dBm} $，超过了KR和LRM规范。

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