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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Delay and Power Monitoring Schemes for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes
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Delay and Power Monitoring Schemes for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes

机译：延迟和功率监控方案，通过主动和待机模式下的电源和阈值电压控制将功耗降至最低

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This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V{sub}(DD) and threshold voltage V{sub}(TH) in active and standby modes. In the active mode, on the basis of delay monitoring results, either V{sub}(DD) control or V{sub}(TH) control is selected to avoid any oscillation problem between them. In V{sub}(DD) control, on the basis of delay monitoring results, V{sub}(DD) is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V{sub}(TH) control, on the basis of power monitoring results, V{sub}(TH) is adjusted so as to maintain a certain switching current I{sub}(sw)/leakage current I{sub}(LEAK) ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I{sub}(SUBTH) to substrate current I{sub}(SUB)) is improved by taking into consideration both the effects of lowering V{sub}(DD) and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I{sub}(SW)/I{sub}(LEAK) ratio in the active mode and 2) detect optimum body bias conditions (I{sub}(SUBTH) = I{sub}(SUB)) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.
机译：本文介绍了新开发的延迟和功率监视方案，该方案通过在活动和待机模式下动态控制电源电压V {sub}（DD）和阈值电压V {sub}（TH）来最大程度地降低功耗。在活动模式下，根据延迟监视结果，选择V {sub}（DD）控制或V {sub}（TH）控制以避免它们之间的任何振荡问题。在V {sub}（DD）控制中，基于延迟监视结果，将V {sub}（DD）调整为保持在芯片能够以给定的时钟频率工作的最小值。在V {sub}（TH）控制中，基于功率监视结果，对V {sub}（TH）进行调整，以维持一定的开关电流I {sub}（sw）/漏电流I {sub}（ LEAK）比率表示最小功耗。在待机模式下，通过同时考虑降低V的影响，可以提高功率监控的精度（通过比较亚阈值电流I {sub}（SUBTH）与衬底电流I {sub}（SUB）来检测最佳车身偏置）。 {sub}（DD）和栅极氧化物泄漏电流的存在的影响。 90纳米CMOS器件的实验结果表明，使用建议的功率监控可成功地将功耗降至最低。为此，它可以做到以下几点：1）在活动模式下保持I {sub}（SW）/ I {sub}（LEAK）比率，以及2）检测最佳车身偏置条件（I {sub}（SUBTH）=相对于待机模式下的实际最小漏电流值，I {sub}（SUB））的误差小于20％。

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