A dynamically reconfigurable SIMD processor for a vision chip

Komuro T.; Kagami S.; Ishikawa M.

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A dynamically reconfigurable SIMD processor for a vision chip

机译：用于视觉芯片的可动态重新配置的SIMD处理器

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Conventional SIMD image processors are very effective for early visual processing because of their parallelism. However, in performing more advanced processing, they exhibit some problems, such as poor performance in global operations and a tradeoff between flexibility of processing and the number of pixels. This paper shows a new architecture and sample algorithms of a vision chip that has the ability to reconfigure its hardware dynamically by chaining processing elements. A prototype chip with 64×64 pixels manufactured using the 0.35-Μm CMOS process is also shown.

机译：传统的SIMD图像处理器由于具有并行性，因此对于早期视觉处理非常有效。但是，在执行更高级的处理时，它们表现出一些问题，例如全局操作中的性能较差以及处理灵活性和像素数之间的权衡。本文展示了一种视觉芯片的新架构和示例算法，该视觉芯片具有通过链接处理元素来动态地重新配置其硬件的能力。还显示了使用0.35-μmCMOS工艺制造的具有64×64像素的原型芯片。

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来源
《IEEE Journal of Solid-State Circuits》 |2004年第1期|p.265-268|共4页
作者
Komuro T.; Kagami S.; Ishikawa M.;
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作者单位

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS integrated circuits; computer vision; digital signal processing chips; image processing equipment; parallel architectures; reconfigurable architectures; 0.35 micron; 64 pixels; CMOS process; SIMD image processors; chaining processing elements; dynamically reco;

机译：CMOS集成电路;计算机视觉;数字信号处理芯片;图像处理设备;并行架构;可重配置架构;0.35微米;64像素;CMOS工艺;SIMD图像处理器;链接处理元件;动态识别;

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专利

1. A Dynamically Reconfigurable SIMD Processor for a Vision Chip [J] . Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa IEEE Journal of Solid-State Circuits . 2004,第1期

机译：用于视觉芯片的可动态重新配置的SIMD处理器
2. PRECISION: A Reconfigurable SIMD/MIMD Coprocessor for Computer Vision Systems-on-Chip [J] . Alejandro Nieto, David L. Vilariño, Victor M. Brea IEEE Transactions on Computers . 2016,第8期

机译：精度：用于计算机视觉片上系统的可重配置SIMD / MIMD协处理器
3. A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network [J] . Shi C., Yang J., Han Y., Solid-State Circuits, IEEE Journal of . 2014,第9期

机译：基于动态可重构混合架构的1000 fps视觉芯片，包括PE阵列处理器和自组织地图神经网络
4. Reconfigurable on-chip SIMD processor architectures for intelligent CMOS camera chips [C] . Fey, D., Hoppe, . 2004

机译：可重配置的片上SIMD处理器架构，用于智能CMOS相机芯片
5. Experimental demonstration of optical router and signal processing functions in dynamically reconfigurable wavelength-division-multiplexed fiber-optic networks. [D] . McGeehan, John Edward. 2005

机译：在动态可重构波分复用光纤网络中光路由器和信号处理功能的实验演示。
6. A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision Control and Signal Processing [O] . Gabriel J. García, Carlos A. Jara, Jorge Pomares, 2014

机译：基于FPGA的传感器系统的调查：面向用于计算机视觉控制和信号处理的智能且可重新配置的低功耗传感器
7. A Dynamically Reconfigurable Architecture Combining Pixel-Level SIMD and Operation-Pipeline Modes for High Frame Rate Visual Processing [O] . Nao Iwata, Shingo Kagami, Koichi Hashimoto 2008

机译：结合像素级SIMD和操作管道模式的动态可重新配置架构，可实现高帧率视觉处理

A dynamically reconfigurable SIMD processor for a vision chip

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