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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider
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A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

机译:具有动态逻辑分频器的13.5mW 5 GHz频率合成器

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The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-Μm CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.
机译:在数千兆赫兹的CMOS锁相环中采用动态分频器,可以在不损害锁相环(PLL)的相位噪声和电源灵敏度的情况下,大幅降低功耗。集成在0.25-Mm CMOS技术中的5 GHz频率合成器显示出13.5 mW的总功耗。分频器结合了常规和扩展的真单相时钟逻辑。振荡器采用轨到轨拓扑,以确保适当的分频器功能。该用于无线LAN应用的PLL可以20 MHz的步长合成5.14和5.70 GHz之间的频率。在整个调谐范围内,在10 MHz偏移处的参考杂散低至-70 dBc,在1 MHz时的相位噪声低于-116 dBc / Hz。

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