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首页> 外文期刊>IEEE Journal of Solid-State Circuits >On the design and characterization of femtoampere current-mode circuits
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On the design and characterization of femtoampere current-mode circuits

机译：飞安电流模式电路的设计与表征

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摘要

In this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also uses a special on-chip sawtooth oscillator to monitor and measure currents down to a few femtoamperes. This way, subpicoampere currents are characterized without driving them off chip and requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is implemented that uses a 100-fF capacitor and a 3.5-fA bias current to achieve a cutoff frequency of 0.5 Hz. A technique for characterizing noise at these currents is also described and verified. Finally, transistor mismatch measurements are provided and discussed. Experimental measurements are shown throughout the paper, obtained from prototypes fabricated in the AMS 0.35-/spl mu/m three-metal two-poly standard CMOS process.
机译：在本文中，我们展示并验证了一种可靠的电路设计技术，该技术基于源电压移位，可用于电流模式信号处理（低至飞安）。该技术涉及特定电流提取器和对数电流分配器，用于获得片上亚皮安电流。它还使用特殊的片上锯齿振荡器来监视和测量低至几飞安的电流。这样，亚皮安电流的特征在于无需将其驱离芯片，也无需复杂的低泄漏设置就需要昂贵的仪器。还引入了特殊的电流镜以可靠地复制这种低电流。例如，实现了一个简单的对数域一阶低通滤波器，该滤波器使用一个100fF电容器和一个3.5fA偏置电流来实现0.5Hz的截止频率。还描述并验证了用于表征这些电流下的噪声的技术。最后，提供并讨论了晶体管失配测量。整个论文中均显示了实验测量结果，这些测量结果是通过AMS 0.35- / spl mu / m三金属二聚标准CMOS工艺制造的原型获得的。

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