A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

Farjad-Rad R.; Dally W.; Hiok-Tiaq Ng; Senthinathan R.; Lee M.-J.E.; Rathi R.; Poulton J.

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A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

机译：低功耗乘法DLL，可在高度集成的数字芯片中生成低抖动的数GHz时钟

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A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-Μm CMOS technology, occupies a total active area of 0.05 mm2 and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of M=4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72×72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk).

机译：描述了一种用于高速片上时钟生成的乘法延迟锁定环（MDLL），该延迟锁定环克服了锁相环（PLL）的缺点，例如抖动累积，电源的高灵敏度和基板噪声。 MDLL设计消除了这些缺点，同时保持了用于多速率频率乘法的PLL的优势。该设计还使用电源调节器和滤波器来进一步减少片上抖动的产生。 MDLL采用0.18-μmCMOS技术实现，总有效面积为0.05 mm2，速度范围为200 MHz至2 GHz，可选择的倍频比为M = 4、5、8、10。完整的合成器，包括输出时钟缓冲器从2.0 GHz的1.8V电源消耗12 mW的功率。这种MDLL体系结构用作集成在72×72 STS-1修饰开关的单个芯片上的时钟倍频器，其抖动为1.73 ps（rms）和13.1 ps（pk-pk）。

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来源
《IEEE Journal of Solid-State Circuits》 |2002年第12期|p.1804-1812|共9页
作者
Farjad-Rad R.; Dally W.; Hiok-Tiaq Ng; Senthinathan R.; Lee M.-J.E.; Rathi R.; Poulton J.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS digital integrated circuits; clocks; delay lock loops; frequency synthesizers; high-speed integrated circuits; jitter; low-power electronics; multiplying circuits; 0.18 micron; 1.8 V; 12 mW; 200 MHz to 2 GHz; CMOS technology; DLL frequency synthesizer; STS-1 groo;

机译：CMOS数字集成电路;时钟;延迟锁定环;频率合成器;高速集成电路;抖动;低功耗电子设备;乘法电路;0.18微米;1.8 V;12 mW;200 MHz至2 GHz;CMOS技术;DLL频率合成器;STS-1 groo;

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专利

1. A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips [J] . Farjad-Rad R., Dally W., Hiok-Tiaq Ng, IEEE Journal of Solid-State Circuits . 2002,第12期

机译：低功耗乘法DLL，可在高度集成的数字芯片中生成低抖动的数GHz时钟
2. A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL [J] . Analog Integrated Circuits and Signal Processing . 2020,第3期

机译：低抖动时钟乘法器使用简单的低功耗ECDLL，在VCDL中具有额外的延迟延迟
3. High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator [J] . K. Ryu, J. Jung, D. H. Jung, IEEE transactions on very large scale integration (VLSI) systems . 2016,第4期

机译：用于基于DLL的时钟发生器的高速，低功耗，高可靠性倍频器
4. A 0.2-2GHz 12mW multiplying DLL for low-jitter clock synthesis in highly-integrated data-communication chips [C] . Farjad-rad, R., Dally, . 2002

机译：0.2-2GHz 12mW乘法DLL，用于高度集成的数据通信芯片中的低抖动时钟合成
5. Low-power low-jitter on-chip clock generation. [D] . Mansuri, Mozhgan. 2003

机译：低功耗，低抖动的片上时钟生成。
6. A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node [O] . Duo Sheng, Min-Rong Hong 2016

机译：用于无线传感器节点的低功耗全数字片上CMOS振荡器
7. Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers [O] . Xiang Gao, Eric A. M. Klumperink, Bram Nauta 2013

机译：低抖动多相时钟生成：DLL与移位寄存器之间的比较

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

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