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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A low-power digital matched filter for direct-sequencespread-spectrum signal acquisition
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A low-power digital matched filter for direct-sequencespread-spectrum signal acquisition

机译:低功率数字匹配滤波器,用于直接序列扩频信号采集

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This paper presents a low-power 128-tap dual-channelndirect-sequence spread-spectrum (DSSS) digital matched-filter chip.nDesign techniques used to reduce the power consumption of the systemninclude latch-based register file filter structure, a high-ratencompression scheme, optimized compressor cells, and semicustom layoutndesign. To further reduce the power consumption and the hardwarenrequirement of the clock tree, a double-edge-triggered clocking schemenis adopted. The proposed chip is fabricated using a 0.8-Μm standardnCMOS process. As the experimental results of the chip indicate, thenmatched filter can operate at 50 MHz and dissipates 184 mW at 5-V supplynvoltage. The supply voltage can be scaled down to 2 V for lower speednapplications. As a consequence, the proposed design has low powernconsumption and can be used for code acquisition of DSSS signals innportable systems
机译:本文介绍了一种低功耗128抽头双通道n序列扩频(DSSS)数字匹配滤波器芯片。n用于降低系统功耗的设计技术n包括基于锁存器的寄存器文件滤波器结构,一种高压缩率方案,优化的压缩机单元和半定制布局。为了进一步降低时钟树的功耗和硬件需求,采用了双沿触发时钟方案。所提出的芯片是使用0.8μmstandardnCMOS工艺制造的。如芯片的实验结果所示,匹配的滤波器可以在50 MHz下工作,并在5V电源电压下耗散184 mW。对于低速应用,电源电压可以降低至2V。结果,所提出的设计具有低功耗,并且可以用于DSSS信号不可移植系统的代码获取

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