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首页> 外文期刊>IEEE Journal of Solid-State Circuits >An adaptive PLL tuning system architecture combining high spectral purity and fast settling time
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An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

机译：自适应PLL调谐系统架构，结合了高频谱纯度和快速建立时间

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摘要

An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.
机译：描述了一种用于高性能调谐系统的自适应锁相环（PLL）架构。该体系结构结合了不同性能方面提出的矛盾要求。环路参数的调整连续发生，无需切换环路滤波器组件，也无需来自调谐系统外部的交互。提出了性能方面（建立时间，相位噪声和杂散信号）与设计变量（环路带宽，相位裕量和参考频率处的环路滤波器衰减）之间的关系，并讨论了新概念的基本权衡。详细描述了自适应PLL的电路实现，该电路已针对在多频带（全局）汽车无线电调谐器IC中使用进行了优化。所实现的调谐系统达到了同类产品中最先进的建立时间和频谱纯度性能（整数N PLL）：信噪比为65 dB，-81以下为100 kHz的伪参考突破信号对于20 MHz的频率步进，dBc和1 ms后3 kHz的残留建立误差。它同时满足了听不见的跳频的速度要求和64 dB的重信噪比规范。

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