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首页> 外文期刊>IEEE Journal of Solid-State Circuits >An adaptive PLL tuning system architecture combining high spectralpurity and fast settling time
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An adaptive PLL tuning system architecture combining high spectralpurity and fast settling time

机译：结合了高光谱纯度和快速建立时间的自适应PLL调谐系统架构

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摘要

An adaptive phase-locked loop (PLL) architecture fornhigh-performance tuning systems is described. The architecture combinesncontradictory requirements posed by different performance aspects.nAdaptation of loop parameters occurs continuously, without switching ofnloop filter components, and without interaction from outside of thentuning system. The relationship of performance aspects (settling time,nphase noise, and spurious signals) to design variables (loop bandwidth,nphase margin, and loop filter attenuation at the reference frequency)nare presented, and the basic tradeoffs of the new concept are discussed.nA circuit implementation of the adaptive PLL, optimized for use in anmultiband (global) car-radio tuner IC, is described in detail. Thenrealized tuning system achieved state-of-the-art settling time andnspectral purity performance in its class (integer-N PLLs): ansignal-to-noise ratio of 65 dB, a 100-kHz spurious referencenbreakthrough signal under -81 dBc, and a residual settling error of 3nkHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfillsnthe speed requirements for inaudible frequency hopping and the heavynsignal-to-noise ratio specification of 64 dB
机译：描述了用于高性能调谐系统的自适应锁相环（PLL）体系结构。该体系结构结合了不同性能方面提出的矛盾要求。循环参数的自适应持续发生，无需切换n环路滤波器组件，也无需来自调谐系统外部的交互。提出了性能方面（建立时间，n相噪声和杂散信号）与设计变量（环路带宽，n相裕度和参考频率处的环路滤波器衰减）之间的关系，并讨论了新概念的基本折衷。详细介绍了针对多频带（全球）汽车无线电调谐器IC优化使用的自适应PLL的电路实现。然后实现的调谐系统在同类产品中（整数N PLL）实现了最先进的建立时间和n光谱纯度：信噪比为65 dB，低于-81 dBc的100kHz杂散参考n突破信号以及1 ms之后的3nkHz残余建立误差，对于20MHz的频率步进。它同时满足听不见的跳频的速度要求和64 dB的重信噪比规范

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