A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on directclock cycle interpolation for “clock on demand”

Saeki T.; Mitsuishi M.; Iwaki H.; Tagishi M.

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A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on directclock cycle interpolation for “clock on demand”

机译：基于直接时钟周期内插的1.3周期锁定时间，非PLL / DLL时钟乘法器，用于“按需时钟”

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摘要

A 1.3-cycle lock-in time, non-PLL/DLL clock multiplier based onndirect clock cycle interpolation is proposed with an array structure ofnshort-circuit-current-suppression interpolators. The circuits have beennfabricated with a 0.25-Μm digital CMOS and operated in any conditionnwhere digital CMOS circuits operate. Measured results have achieved 1.3nclock cycle lock time and cycle-to-cycle jitter suppressionncharacteristics. The circuits have been verified in 622-Mb/s clock andndata recovery that satisfied the ITU-T G.958 jitter tolerancenspecification

机译：提出了一种基于n个直接时钟周期内插的1.3周期锁定时间，非PLL / DLL时钟乘法器，该结构具有n个短路电流抑制内插器的阵列结构。这些电路已经用0.25μm的数字CMOS制成，并且可以在数字CMOS电路运行的任何条件下运行。测量结果获得了1.3nclock的周期锁定时间和周期间抖动抑制特性。电路已通过622-Mb / s的时钟和n数据恢复验证，符合ITU-T G.958抖动容限n规范

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来源
《IEEE Journal of Solid-State Circuits》 |2000年第11期|p.1581-1590|共10页
作者
Saeki T.; Mitsuishi M.; Iwaki H.; Tagishi M.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS digital integrated circuits; clocks; interpolation; multiplying circuits; timing jitter; 0.25 mum; 1.3-cycle lock-in time; 622 Mbit/s; ITU-T G.958 jitter tolerance specification; array structure; clock cycle lock time; clock on demand; clock recovery; cycle-to-c;

机译：CMOS数字集成电路;时钟;内插;乘法电路;定时抖动;0.25μm;1.3周期锁定时间;622 Mbit / s;ITU-T G.958抖动容限规范;阵列结构;时钟周期锁定时间;时钟按需;时钟恢复;循环到c;

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专利

1. A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand" [J] . Saeki T., Mitsuishi M. IEEE Journal of Solid-State Circuits . 2000,第11期

机译：基于直接时钟周期内插的1.3周期锁定时间，非PLL / DLL时钟乘法器，用于“按需时钟”
2. A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance [J] . Helal B. M., Straayer M. Z., Wei G.-Y., IEEE Journal of Solid-State Circuits . 2008,第4期

机译：一个基于MDLL的高度数字化时钟乘法器，利用自扰时间数字转换器实现亚皮秒级抖动性能
3. A DLL based clock multiplier using rotational DCDL and PRNG for spur reduction [J] . Noh Jinseop, Jee Dong-Woo Annals of the American Thoracic Society . 2019,第3期

机译：一种基于DLL的时钟倍增器，使用旋转DCDL和PRNG进行刺激
4. A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand" [C] . Saeki, T., Mitsuishi, . 2000

机译：基于直接时钟周期内插的1.3周期锁定时间，非PLL / DLL抖动抑制时钟乘法器，用于“按需时钟”
5. Clock multiplier unit and clock data recovery circuit for 10Gb/s broadband communication in 0.18mum CMOS. [D] . Cao, Jun. 2003

机译：时钟乘法器单元和时钟数据恢复电路，用于0.18mum CMOS中的10Gb / s宽带通信。
6. Focus: Clocks and Cycles: Clocks and Cycles [O] . Devon Wasche, Ian Gonzalez 2019

机译：重点：时钟和周期：时钟和周期
7. On Jitter due to Delay Cell Mismatch in DLL-based Clock Multipliers [O] . van de Beek R.C.H., Klumperink Eric A.M., Vaucher C.S., 2002

机译：在基于DLL的时钟倍频器中由于延迟单元不匹配而引起的抖动

A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on directclock cycle interpolation for “clock on demand”

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