A novel clock network composed of multiple synchronized phase-locked loops is analyzed, implemented, and tested. Undesirable large-signal stable (mode-locked) states dictate the transfer characteristic of the phase detectors; a matrix formulation of the linearized system allows direct calculation of system poles for any desired oscillator configuration. A 16-oscillator 1.3-GHz distributed clock network in 0.35-/spl mu/m CMOS is presented here.
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机译：分析，实现和测试了由多个同步锁相环组成的新型时钟网络。不良的大信号稳定（锁模）状态决定了鉴相器的传输特性。线性化系统的矩阵公式可直接为任何所需的振荡器配置计算系统极点。此处介绍了采用0.35- / spl mu / m CMOS的16振荡器1.3-GHz分布式时钟网络。
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