Design and implementation of a 5×5 trits multiplier in aquasi-adiabatic ternary CMOS logic

Mateo D.; Rubio A.

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Design and implementation of a 5×5 trits multiplier in aquasi-adiabatic ternary CMOS logic

机译：准绝热三元CMOS逻辑中5×5 Trits乘法器的设计与实现

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Adiabatic switching is a technique to design low-power digitalnIC's. Fully adiabatic logics have expensive silicon area requirements.nTo solve this drawback, a quasi-adiabatic ternary logic is proposed. Itsnbasis is presented, and to validate its performance, a 5×5 ternaryndigit multiplier is designed and implemented in a 0.7-Μm CMOSntechnology. Results show a satisfactory power saving with respect tonconventional and other quasi-adiabatic binary multipliers, and andecrease of the area needed with respect to a fully adiabatic binary one

机译：绝热开关是一种设计低功耗数字IC的技术。完全绝热逻辑对硅面积的要求很高。为了解决这个缺点，提出了一种准绝热三元逻辑。介绍了其基本原理，并为验证其性能，设计了一种5×5三进制乘法器，并以0.7μmCMOSn技术实现。结果表明，相对于传统的和其他绝热的二进制乘法器，节电效果令人满意，并且相对于完全绝热的二进制乘法器，所需面积减小了。

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来源
《IEEE Journal of Solid-State Circuits》 |1998年第7期|p.1111-1116|共6页
作者
Mateo D.; Rubio A.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS logic circuits; integrated circuit design; multiplying circuits; ternary logic; 0.7 micron; CMOS technology; area requirements; power saving; quasi-adiabatic ternary CMOS logic; ternary digit multiplier;

机译：CMOS逻辑电路;集成电路设计;乘法电路;三进制逻辑;0.7微米;CMOS技术;面积要求;省电;准绝热三进制CMOS逻辑;三位数乘法器;

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1. Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic [J] . Mateo D., Rubio A. IEEE Journal of Solid-State Circuits . 1998,第7期

机译：准绝热三元CMOS逻辑中5 / spl times / 5 trits乘法器的设计与实现
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4. Implementation of a 5X5 trits multiplier in a quasi-adiabatic ternary CMOS logic [C] . Diego Mateo, Antonio Rubio Proceedings of the 23rd European solid-state circuits conference . 1997

机译：在准绝热三元CMOS逻辑中实现5X5 Trits乘法器
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Design and implementation of a 5×5 trits multiplier in aquasi-adiabatic ternary CMOS logic

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