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首页> 外文期刊>IEEE Journal of Solid-State Circuits >The impact of scaling down to deep submicron on CMOS RF circuits
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The impact of scaling down to deep submicron on CMOS RF circuits

机译:缩小至深亚微米对CMOS RF电路的影响

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摘要

Recent papers reporting CMOS RF building blocks have aroused greatnexpectations for RF receivers using deep-submicron technologies. Thisnpaper examines the trend in CMOS scaling, in order to establish thenrequired current levels and achievable performance for different featurensizes, if robust, easily manufacturable designs are to be implementednfor cellular applications. The boundary conditions (system-levelnconstraints) for such designs, in terms of the number of trimmed andnuntrimmed external components and the roles they play in relaxing activencircuit requirements, are emphasized throughout to make comparison ofnactive RF circuits meaningful. At 1 GHz, 0.25-Μm CMOS appears to benthe threshold for robust, low-NF RF front ends with current consumptionncompetitive with today's BJT implementations
机译:最近报道CMOS RF构造块的论文引起了使用深亚微米技术的RF接收器的极大关注。本白皮书探讨了CMOS缩放的趋势,以便确定适用于蜂窝应用的健壮,易于制造的设计,从而确定不同功能尺寸所需的电流水平和可实现的性能。整个过程中都强调了此类设计的边界条件(系统级约束),这些边界条件包括经过修剪和未修剪的外部组件的数量以及它们在放宽有源电路要求中所扮演的角色,从而使无源RF电路的比较有意义。在1 GHz频率下,0.25-μmCMOS似乎已成为坚固耐用的低NF RF前端的最低阈值,且电流消耗与当今的BJT实现方案不相上下。

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