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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 3.3-V power adaptive 1244/622/155 Mbit/s transceiver for ATM, SONET/SDH
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A 3.3-V power adaptive 1244/622/155 Mbit/s transceiver for ATM, SONET/SDH

机译：用于ATM，SONET / SDH的3.3V功率自适应1244/622/155 Mbit / s收发器

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摘要

This paper presents the implementation of a multirate 155-, 622-, or 1244-Mbit/s transceiver for ATM and SDH/SONET in a 0.5-/spl mu/m BiCMOS. The internal high-speed clock generation is based on PLL's with 1.24-GHz VCO's. The solutions presented here allow us to get rid of the external trimming of the free-running frequency of VCO. The automatic adjustment of the clock and data recovery PLL VCO free running is performed, and thus, increases the robustness of the RX function without expenses in manual trimming. The architecture of this transceiver is thought to enable the full-frequency Wafer test of the whole core by specific loop-back modes. As the same core is used for 155-Mbit/s, 622-Mbit/s, and 1.2-Gbit/s power adaptation techniques are implemented which lead to a 660-mW consumption for 155-Mbit/s operation and 1.1 W for 1.24 Gbits/s. A specific digitally programmable power adaptive ECL cell library concept is presented. Noise precautions are also described, as well as an analog HDL top-down methodology developed by SGS-Thomson Central R&D to short-down the development time and increase reusability.
机译：本文介绍了在0.5- / spl mu / m BiCMOS中用于ATM和SDH / SONET的多速率155-，622-或1244-Mbit / s收发器的实现。内部高速时钟生成基于具有1.24 GHz VCO的PLL。这里介绍的解决方案使我们摆脱了VCO自由运行频率的外部调整。时钟和数据恢复PLL VCO自由运行的自动调整得以执行，因此无需手动调整即可增加RX功能的鲁棒性。该收发器的架构被认为可以通过特定的环回模式实现整个内核的全频Wafer测试。由于相同的内核用于155 Mbit / s，622 Mbit / s和1.2 Gbit / s的功率自适应技术，因此实现了155 Mbit / s的工作功耗为660 mW和1.24的功耗为1.1 W千兆位/秒提出了一种特定的数字可编程功率自适应ECL单元库概念。还介绍了噪声预防措施，以及SGS-Thomson Central R＆D开发的模拟HDL自顶向下方法，以缩短开发时间并提高可重复使用性。

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