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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers
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Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

机译：在同时开关的CMOS输出缓冲器中形成阻尼LRC寄生电路

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摘要

Several techniques to reduce the ground bounce effect in CMOS chips are described. The effective width of the predrive and final driver of a CMOS output buffer is automatically adjusted to compensate for process, voltage, and temperature (PVT) variations. The slew rate of the predrive nodes is controlled by introducing a digitally weighted capacitance. Finally, a compensated active resistance is inserted into both the power and ground leads to further dampen the oscillations. These techniques allow the buffer to behave uniformly over the entire PVT range. Measurements of a 0.5-/spl mu/m CMOS test chip have demonstrated that these new buffers generate 2.5/spl times/ less ground bounce when compared to conventional buffers. An external resistance is required to set a reference current.
机译：描述了几种减少CMOS芯片中接地反弹效应的技术。 CMOS输出缓冲器的预驱动器和最终驱动器的有效宽度会自动调整，以补偿工艺，电压和温度（PVT）的变化。预驱动节点的压摆率通过引入数字加权电容来控制。最后，将补偿的有源电阻插入电源线和地线中，以进一步抑制振荡。这些技术使缓冲器在整个PVT范围内表现均匀。对0.5- / splμm/ m CMOS测试芯片的测量表明，与传统缓冲器相比，这些新型缓冲器产生的接地跳动为2.5 / spl次/更少。需要外部电阻来设置参考电流。

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