This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-/spl mu/m CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit.
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机译：本文提出了一种使用匹配延迟采样技术对高速串行数据进行解复用和同步的方案和电路。通过同时通过两个不同的延迟抽头来传播数据和时钟信号，采样器实现了非常精细的采样分辨率，这取决于数据和时钟延迟之间的差异。匹配延迟采样器的这种高分辨率采样功能可用于过采样数据恢复电路。使用匹配延迟采样技术的数据恢复电路已经以1.2- / spl mu / m CMOS技术进行了设计和制造。该芯片已经过417 Mb / s [2.4 ns不归零（NRZ）的输入数据]测试，并将串行输入数据多路分解为四个104 Mb / s（9.6 ns NRZ）输出流，在4 V电源下的功耗为800 mW 。在恢复数据时，基于从数字相位控制电路提取的信息，以输入数据的相位跟踪以数据频率的1/4运行的采样时钟。
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