A fast resolving BiNMOS synchronizer for parallel processor interconnect

Jex J.; Dike C.

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A fast resolving BiNMOS synchronizer for parallel processor interconnect

机译：用于并行处理器互连的快速解析BiNMOS同步器

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摘要

The design, testing, and application of a BiNMOS metastability resolving synchronizer is described. High speed signaling requires multiple clock cycle metastability settling time. The integrated circuit provides low tau (fast resolution) and is considered one of the fastest synchronizers available to date. The circuit reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle. High gain-bandwidth product is accomplished with n-p-n transistors driving a cross-coupled inverter latch with reduced node capacitance. Longer settling time is provided by omitting metastability immune circuitry and using a parallel staged synchronizer.

机译：描述了BiNMOS亚稳解析同步器的设计，测试和应用。高速信令需要多个时钟周期亚稳态建立时间。该集成电路具有低tau（快速分辨率）的特性，被认为是迄今为止可用的最快的同步器之一。该电路以高增益带宽乘积和每个时钟周期更长的建立时间来减少亚稳故障。高增益带宽乘积可通过n-p-n晶体管驱动交叉耦合的反相器锁存器来降低节点电容来实现。通过省略亚稳定性免疫电路并使用并行分段同步器，可以提供更长的建立时间。

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来源
《IEEE Journal of Solid-State Circuits》 |1995年第2期|P.133-139|共7页
作者
Jex J.; Dike C.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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A fast resolving BiNMOS synchronizer for parallel processor interconnect

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