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首页> 外文期刊>Solid-State Circuits Magazine, IEEE >Trends and New Opportunities in Digital Phase-Locked Loop Design: Design Principles, Key Overheads, and New Opportunities in This Emerging Architecture
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Trends and New Opportunities in Digital Phase-Locked Loop Design: Design Principles, Key Overheads, and New Opportunities in This Emerging Architecture

机译：数字锁相循环设计中的趋势和新机遇：设计原则，关键开销和本新兴建筑的新机遇

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摘要

Phase-locked loop (PLL)-based frequency synthesizers are pervasively utilized in almost every electronic system for generating welldefined clock frequencies of interest. For instance, in a modern wireless transceiver, a radio-frequency (RF) synthesizer is typically used as a local oscillator to upconvert/downconvert the desired signal to and from the proper communication bands. A similar utilization of RF PLL can be seen in a wireline transceiver, which modulates and demodulates the data symbol at a precise frequency and phase. In addition to RF applications, PLL is also commonly used in baseband and digital circuitry, such as generating a sampling clock for switched-capacitor circuits and clocking the sequential logic of the digital circuitry. As the complexity of the modern system-onchip (SoC) platform continues to grow, it is likely to require numerous highperformance PLLs. Moreover, interference coupling through the same silicon substrate is exacerbated. As a result, the low implementation (area and power) cost, high reconfigurability, resilience over interferences, and reduced design time of a PLL have become increasingly important in light of this new trend.
机译：基于锁相环（PLL）的频率合成器在几乎每个电子系统中被普及用于产生井下义的时钟频率的感兴趣的时钟。例如，在现代无线收发器中，射频（RF）合成器通常用作本地振荡器，以将所需信号上方与适当的通信频带上方的转换/下变频。在有线收发器中可以看到RF PLL的类似利用，其在精确的频率和相位调制和解调数据符号。除了RF应用之外，PLL还通常用于基带和数字电路，例如为用于开关电容器电路的采样时钟和数字电路的顺序逻辑。随着现代系统onchip（SoC）平台的复杂性继续增长，它可能需要众多高度的PLDS。此外，通过相同的硅衬底的干涉耦合加剧。结果，鉴于这种新趋势，低实现（面积和功率）成本，高度的重新配置性，恢复性，以及PLL的设计时间越来越重要。

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