Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Beckers Arnout; Jazaeri Farzan; Bohuslayskyi Heorhii; Hutin Louis; De Franceschi Silvano; Enz Christian

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Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

机译：低温下28 nm FDSOI CMOS技术的表征和建模

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This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

机译：本文介绍了在低温条件下运行的商用28nm FDSOI CMOS工艺的广泛表征和建模。讨论了影响该技术的重要低温现象。使用面向设计的简化EKV模型，可以在很宽的温度范围（室温低至4.2 K）中对包括偏心的低温传递特性进行建模。使用最近建议的基于输出电导的方法，分别从低至1.4 K和4.2 K的直流测量中提取了长窄器件和短窄器件中自由载流子迁移率随温度变化的趋势。在长pMOS上观察到低温温度引起的迁移率降低，从而导致最大空穴迁移率在77 K附近。这项工作为使用基于物理的低温紧凑模型制备工业设计套件奠定了基础，这是成功进行协整的前提硅量子位的FDSOI CMOS电路的工作原理是深低温。

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来源
《Solid-State Electronics》 |2019年第9期|106-115|共10页
作者
Beckers Arnout; Jazaeri Farzan; Bohuslayskyi Heorhii; Hutin Louis; De Franceschi Silvano; Enz Christian;
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作者单位

Ecole Polytech Fed Lausanne, Integrated Circuits Lab ICLAB, Lausanne, Switzerland;

Ecole Polytech Fed Lausanne, Integrated Circuits Lab ICLAB, Lausanne, Switzerland;

CEA Leti, Grenoble, France;

CEA Leti, Grenoble, France;

CEA Leti, Grenoble, France;

Ecole Polytech Fed Lausanne, Integrated Circuits Lab ICLAB, Lausanne, Switzerland;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
原文格式 PDF
正文语种 eng
中图分类
关键词
28 nm FDSOI; Characterization; Cryogenic CMOS; Cryogenic MOSFET; Double-gate; Low temperature; Mobility; Modeling; 4.2 K;

机译：28 nm FDSOI;表征;低温CMOS;低温MOSFET;双栅;低温;迁移率;建模;4.2 K;

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1. Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures [J] . Beckers Arnout, Jazaeri Farzan, Bohuslayskyi Heorhii, Solid-State Electronics . 2019,第Sepa期

机译：28-NM FDSOI CMOS技术对低温温度的表征与建模
2. Cryogenic Characterization of 22-nm FDSOI CMOS Technology for Quantum Computing ICs [J] . Bonen S., Alakusu U., Duan Y., IEEE Electron Device Letters . 2019,第1期

机译：用于量子计算IC的22nm FDSOI CMOS技术的低温特性
3. Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes [J] . Robert Polster, Yvain Thonnart, Guillaume Waltener, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2016,第12期

机译：65 nm CMOS和28 nm FDSOI技术节点中硅光子链路的效率优化
4. Nanometer CMOS Characterization and Compact Modeling at Deep-Cryogenic Temperatures [C] . R. M. Incandela, L. Song, H. A. R. Homulle, European Solid-State Device Research Conference . 2017

机译：深冷温度下的纳米CMOS表征和紧凑型造型
5. Design, implementation and characterization of temperature compensated SAW resonators in CMOS technology for RF oscillators. [D] . Nordin, Anis Nurashikin. 2008

机译：CMOS技术中用于RF振荡器的温度补偿SAW谐振器的设计，实现和表征。
6. Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process [O] . Ruibo Chen, Hongxia Liu, Wenqiang Song, 2020

机译：具有嵌入式PMOSFET的鲁棒和锁定的免疫LVTSCR器件用于28 nm CMOS过程中的ESD保护
7. Modeling of an integrated active feedback preamplifier in a 025 mu m CMOS technology at cryogenic temperatures [O] . Saramad, Shahyar, Anelli, G, Bucher, M, 2003

机译：在低温下以025μmCMOS技术对集成有源反馈前置放大器进行建模

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

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