In the past 30 years interconnect evolved from a single layer of Al deposited by evaporation to multiple levels of sandwiched Ti/Al-Cu/TiN metal layers deposited by sophisticated magnetron sputtering and connected by Al or W plugs through via holes. Dielectric insulator evolved from low-pressure chemical vapor deposited (LPCVD) SiO_2 film to high density plasma enhanced (HDP CVD) low temperature film for multilevel structures. The development of chemical mechanical polishing (CMP) allowed the building of seemingly unlimited number of levels of interconnects. Yet, with such astonishing advancement the progress of interconnect technology seems to fall short of the expectations from high performance circuits and at each technology node interconnect delays become a higher percentage of the total circuit delay. New materials such as Cu and low-K dielectric insulators are being developed to relieve the performance bottleneck and new structures such as dual-damascene are being investigated to simplify interconnect processes. These measures, assuming their success, will slow the cost escalation but will not provide long term solutions, since materials limits for lower resistivity and dielectric constant will be reached and further reduction will not be feasible. Is a revolution for interconnect technology imminently pending and what will it be?
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