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UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime

机译：UTBB SOI MOSFET模拟量的品质因数：地平面和非对称双栅极机制的影响

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摘要

In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, sub-threshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects.
机译：在这项工作中，我们研究了地平面（GP）对超薄体和薄埋氧化层（UTBB）SOI MOSFET的模拟品质因数（FoM）的影响。基于实验设备，考虑了n型和p型GP的配置，并与标准的非GP基板进行了比较。在标准的单门（SG）方案中，GP实施对模拟FoM的影响（与略高的机身系数和改善的门-通道耦合有关）可以忽略不计。此外，与无GP和n-GP衬底相比，p-GP的实现方式允许在高频下具有更高的固有增益。此外，我们证明非对称双栅极（ADG）（即，前栅极至后栅极/衬底的连接）方案的应用可以更好地控制短沟道效应，如漏极引起的势垒降低，亚阈值斜率和阈值电压控制，因为改善了栅极到通道的耦合。显示了ADG模式的应用可以增强模拟FoM，例如跨导，驱动电流和UTBB SOI MOSFET的固有增益。最后，仿真预测，在整个动态工作范围内，可以通过ADG模式提供的模拟FoM有所改善。此外，ADG模式消除了高频基板耦合效应。

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  • 来源
    《Solid-State Electronics》 |2013年第12期|56-64|共9页
  • 作者

    M.K. Md Arshad; S. Makovejev; S. Olsen; F. Andrieu; J.-P. Raskin; D. Flandre; V. Kilchytska;

  • 作者单位

    ICTEAM, Universite catholique de Louvain, 1348 Louvain-la-Neuve, Belgium,Universiti Malaysia Perils, Sch. of Microelectronic Eng, 01000 Kangar, Perlis, Malaysia;

    School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne, UK;

    School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne, UK;

    CEA-Leti M1NATEC 17, Rue des Martyrs, 38054 Grenoble, France;

    ICTEAM, Universite catholique de Louvain, 1348 Louvain-la-Neuve, Belgium;

    ICTEAM, Universite catholique de Louvain, 1348 Louvain-la-Neuve, Belgium;

    ICTEAM, Universite catholique de Louvain, 1348 Louvain-la-Neuve, Belgium;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Ultra-thin body and thin buried oxide FD; SOI MOSFETs; Analog figures of merit; Asymmetrical double gate; Ground plane (GP) implementation;

    机译：超薄机身和薄埋氧化物FD;SOI MOSFET;模拟品质因数;不对称双闸接地平面（GP）实施;

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