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首页> 外文会议>IEEE Regional Symposium on Micro and Nano Electronics >Impact of high-k dielectric on the digital and analog performance on emulation of double-gate UTBB SOI MOSFETs with different ground plane structures
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Impact of high-k dielectric on the digital and analog performance on emulation of double-gate UTBB SOI MOSFETs with different ground plane structures

机译：高k电介质对具有不同接地层结构的双栅极UTBB SOI MOSFET的仿真的数字和模拟性能的影响

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摘要

In this work, we investigate the impact of using different gate dielectric materials i.e HfO2 and Si3N4 as compared to the conventional SiO2 with equivalent oxide thickness (EOT) of 1.2 nm on the digital and analog performance of UTBB SOI MOSFETs of 10 nm gate length with different ground plane (GP) structures under the double-gate (DG) operation-mode by numerical simulations. It is found that Si3N4 provides good digital and analog performance in terms of lower DIBL and higher voltage gain, Av. Meanwhile, GP-A structure which employed p+ doping under the source and drain regions beneath the BOX is able to provide not only high Av but also a stable gain throughout the frequency range as compared to other GP structures. Thus, the configuration of GP-A structure with Si3N4 as the high-k materials is proposed for the design of analog and RF circuits.
机译：在这项工作中，我们研究了使用不同的栅极介电材料（即HfO2和Si3N4）与传统SiO2（等效氧化物厚度（EOT）为1.2 nm）相比对10 nm栅极长度的UTBB SOI MOSFET的数字和模拟性能的影响。通过数值模拟研究了双栅极（DG）工作模式下的不同接地平面（GP）结构。发现Si3N4在较低的DIBL和较高的电压增益Av方面提供了良好的数字和模拟性能。同时，与其他GP结构相比，在BOX下方的源极和漏极区域下采用p +掺杂的GP-A结构不仅能够提供高Av，而且在整个频率范围内都能提供稳定的增益。因此，提出了以Si 3 N 4作为高k材料的GP-A结构的配置，以用于模拟和RF电路的设计。

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