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Test Conference, 2004. Proceedings. ITC 2004
Test Conference, 2004. Proceedings. ITC 2004
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1.
Trends in manufacturing test methods and their implications
机译:
制造测试方法的趋势及其影响
作者:
Kundu S.
;
Mak T.M.
;
Galivanche R.
会议名称:
《》
|
2004年
关键词:
design for testability;
system-on-chip;
microprocessor chips;
manufacturing test methods;
product quality;
recurring cost;
nonrecurring cost;
time to market;
DFT requirements;
tester requirements;
semiconductors chips;
volatile memory;
nonvolatile memory;
PLD;
FPGA;
ASIC;
SOC;
MEM;
processors;
2.
Use of embedded sensors for built-in-test RF circuits
机译:
将嵌入式传感器用于内置测试RF电路
作者:
Bhattacharya S.
;
Chatterjee A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
microwave integrated circuits;
integrated circuit testing;
embedded sensors;
built-in-test RF circuits;
on-chip RF circuits;
microwave circuits;
circuit integration;
RF device-under-test;
manufacturing test;
DC signals;
target test specification;
sinusoidal stimulus;
3.
Z-DFD: design-for-diagnosability based on the concept of Z-detection
机译:
Z-DFD:基于Z检测概念的可诊断性设计
作者:
Pomeranz I.
;
Venkataraman S.
;
Reddy S.M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
fault simulation;
circuit complexity;
circuit simulation;
combinational circuits;
logic design;
logic testing;
benchmark testing;
design for diagnosability;
fault diagnosis;
z -detection;
fault simulation;
benchmark circuits;
circuit complexity;
observation points;
fault pairs;
combinational circuits;
4.
A code-less BIST processor for embedded test and in-system configuration of boards and systems
机译:
用于板卡和系统的嵌入式测试以及系统内配置的无代码BIST处理器
作者:
Clark C.J.
;
Ricchetti M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
field programmable gate arrays;
built-in self test;
logic testing;
logic design;
microprocessor chips;
printed circuit design;
printed circuit testing;
code less BIST processor;
built-in self-test;
embedded test;
system FPGA configuration;
system BIST architecture;
product test;
IP design;
printed circuit testing;
printed circuit design;
5.
A computationally efficient method for accurate spectral testing without requiring coherent sampling
机译:
一种计算有效的方法,无需相干采样即可进行准确的光谱测试
作者:
Zhongjun Yu
;
Degang Chen
;
Geiger R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
spectral analysis;
fast Fourier transforms;
computational complexity;
sampling methods;
ubiquitous computing;
spectral testing;
coherent sampling;
FFT;
fast Fourier transform;
periodic signals;
computational complexity;
extensive controlled simulation;
signal frequency;
signal phase noise;
additive noise;
signal amplitude;
statistical analysis;
noise free environment;
ubiquitous method;
windowing techniques;
6.
A critical path selection method for delay testing
机译:
延迟测试的关键路径选择方法
作者:
Padmanaban S.
;
Tragoudas S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
decision diagrams;
iterative methods;
critical path selection method;
delay testing;
path delay faults;
path intensive circuits;
decision diagrams;
untestable faults;
ISCAS85 benchmarks;
ISCAS89 benchmarks;
ITC99 benchmarks;
iterative methods;
7.
A DFT technique for delay fault testability and diagnostics in 32-bit high performance CMOS ALUs
机译:
DFT技术用于32位高性能CMOS ALU中的延迟故障可测试性和诊断
作者:
Chatterjee B.
;
Sachdev M.
;
Keshavarzi A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
CMOS digital integrated circuits;
integrated circuit testing;
integrated circuit reliability;
microprocessor chips;
fault simulation;
DFT technique;
delay fault testability;
fault diagnostics;
digital CMOS circuit design;
32-bit high performance ALU;
aggressive technology scaling;
multigigahertz microprocessors;
IC testing;
IC reliability;
delay fault detection;
parametric failures;
energy-delay tradeoffs;
fault simulation;
180 to 65 nm;
8.
A high-resolution flash time-to-digital converter and calibration scheme
机译:
高分辨率闪光时间数字转换器和校准方案
作者:
Levine P.M.
;
Roberts G.W.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
CMOS integrated circuits;
integrated circuit noise;
timing circuits;
timing jitter;
calibration;
time measurement;
flip-flops;
integrated circuit measurement;
high resolution flash time-to-digital converter;
on-chip timing measurement systems;
high speed operation;
clock jitter;
integrated circuits;
flip flops;
time quantization;
additive temporal noise;
CMOS process;
delay lock loops;
timing measurement;
5 ps;
14 ps;
0.18 micron;
9.
A high-throughput 5 Gbps timing and jitter test module featuring localized processing
机译:
高吞吐量5 Gbps定时和抖动测试模块,具有本地化处理功能
作者:
Hafed M.M.
;
Chan A.H.
;
Duerden G.
;
Pishdad B.
;
Tam C.
;
Laberge S.
;
Roberts G.W.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
timing;
jitter;
integrated circuit measurement;
integrated circuit testing;
automatic test equipment;
design for testability;
current-mode logic;
timing test module;
jitter test module;
timing test system;
jitter test system;
integrated circuit measurement methods;
localized test result processing;
timing measurement units;
timing generation units;
hardware digital processing units;
parameter extraction;
component invariant vernier delay measurement circuit;
linear programmable delay circuitry;
LVDS;
CML highspeed digital interface standards;
device under test board;
relative delay generation resolution;
autonomous testing;
platform independent pass-fail testing;
5 Gbit/s;
3 ps;
10.
A holistic parallel and hierarchical approach towards design-for-test
机译:
面向测试设计的整体并行和分层方法
作者:
Ravikumar C.P.
;
Hetherington G.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
application specific integrated circuits;
automatic test pattern generation;
built-in self test;
logic gates;
holistic parallel approach;
hierarchical approach;
design for test;
ATPG;
memory BIST;
ASIC products;
multimillion gate designs;
pattern generation;
pattern verification;
DFT;
run time impact minimization;
11.
A new probing technique for high-speed/high-density printed circuit boards
机译:
高速/高密度印刷电路板的新探测技术
作者:
Parker K.P.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
printed circuit testing;
probing technique;
high speed printed circuit boards;
high density printed circuit boards;
design for test;
in-circuit testing;
high speed circuitry;
gigabit logic boards;
DFT rules;
12.
Active tester interface unit design for data collection
机译:
主动测试仪接口单元设计,用于数据收集
作者:
Sivaram A.T.
;
Pierra P.
;
Sheibani S.
;
Nancy Wang-Lee
;
Solorzano J.E.
;
Tran L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
electronic engineering computing;
active tester interface unit design;
data collection;
device characterization;
ATE;
oscilloscopes;
time interval analyzers;
device performance boards;
production testing;
pll jitter;
clock frequency measurements;
source synchronous busses;
output to output AC measurements;
64-pin bus device;
unique performance board design;
embedded resistors;
high speed muxes;
device under test;
high speed devices;
13.
Affordable and effective screening of delay defects in ASICs using the inline resistance fault model
机译:
使用在线电阻故障模型可经济有效地筛查ASIC中的延迟缺陷
作者:
Benware B.
;
Lu C.
;
Van Slyke J.
;
Prabhu Krishnamurthy
;
Madge R.
;
Keim M.
;
Kassab M.
;
Rajski J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
application specific integrated circuits;
automatic test pattern generation;
integrated circuit testing;
integrated circuit modelling;
fault diagnosis;
delays;
transition delay fault testing;
ASIC;
inline resistance fault model;
very deep submicron technology;
timing failures;
transition delay fault model;
test patterns;
ATPG;
IDDQ;
statistical post processing;
multiple test coverage metrics;
14.
An automated, complete, structural test solution for SERDES
机译:
SERDES的自动化,完整的结构测试解决方案
作者:
Sunter S.
;
Roy A.
;
Cote J.-F.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
jitter;
built-in self test;
logic testing;
boundary scan testing;
field programmable gate arrays;
error statistics;
gigahertz serialization;
gigahertz deserialization;
inter-chip data transmission technique;
inter-board data transmission technique;
signal integrity;
bit error rate;
production testing;
picosecond jitter testing;
off-chip jitter;
rise-fall time measurement;
hardware complexity;
onchip measurement technique;
delay line jitter;
jitter test technique;
FPGA;
signal eye test;
high speed circuit;
all-digital technique;
logic BIST;
boundary scan testing;
15.
An optimized DFT and test pattern generation strategy for an Intel high performance microprocessor
机译:
针对英特尔高性能微处理器的优化DFT和测试模式生成策略
作者:
Wu D.M.
;
Lin M.
;
Reddy M.
;
Jaber T.
;
Sabbavarapu A.
;
Thatcher L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
automatic test pattern generation;
microprocessor chips;
integrated circuit testing;
integrated circuit design;
DFT architecture;
test pattern generation;
Intel high performance microprocessor;
ATPG techniques;
return on investment;
high volume manufacturing test environment;
16.
An SOC test integration platform and its industrial realization
机译:
SOC测试集成平台及其产业化实现
作者:
Kuo-Liang Cheng
;
Jing-Reng Huang
;
Chih-Wea Wang
;
Chih-Yen Lo
;
Li-Ming Denq
;
Chih-Tsun Huang
;
Cheng-Wen Wu
;
Shin-Wei Hung
;
Jye-Yuan Lee
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
boundary scan testing;
scheduling;
integrated circuit design;
integrated circuit testing;
integrated circuit manufacture;
SOC test integration platform;
industrial realization;
system on chip;
test scheduling method;
test access mechanism;
IO resource constraints;
test wrapper architecture;
scan test;
short test integration cost;
chip fabrication;
chip design;
timing;
functional test;
17.
An SRAM weak cell fault model and a DFT technique with a programmable detection threshold
机译:
具有可编程检测阈值的SRAM弱单元故障模型和DFT技术
作者:
Pavlov A.
;
Sachdev M.
;
Pineda de Gyvez J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
SRAM chips;
design for testability;
integrated circuit design;
integrated circuit testing;
fault diagnosis;
sensitivity analysis;
integrated circuit modelling;
SRAM cell stability fault model;
programmable detection threshold;
subtle manufacturing defects;
weak cell detection;
sensitivity analysis;
digitally programmable DFT technique;
design for testability;
embedded SRAM;
18.
Application-dependent diagnosis of FPGAs
机译:
FPGA的基于应用的诊断
作者:
Baradaran Tahoori M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
field programmable gate arrays;
logic testing;
fault diagnosis;
application dependent diagnosis;
FPGA;
fault diagnosis;
logic blocks;
application dependent detection methods;
bridging fault identification;
open fault identification;
stuck-at fault identification;
single functional fault;
test configurations;
interconnect diagnosis;
logic diagnosis;
19.
Architectures of increased availability wireless sensor network nodes
机译:
可用性更高的无线传感器网络节点的体系结构
作者:
Man Wah Chiang
;
Zilic Z.
;
Radecka K.
;
Chenard J.-S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
wireless sensor networks;
telecommunication network reliability;
protocols;
microcontrollers;
wireless sensor network nodes;
low energy consumption;
network reliability;
network serviceability;
redundant nodes;
control protocols;
remote testing;
onboard test infrastructure;
sensor node infrastructure;
standard JTAG chains;
scalable architectures;
COTS components;
microcontroller;
20.
Automatic delay calibration method for multi-channel CMOS formatter
机译:
多通道CMOS格式化器的自动延迟校准方法
作者:
Syed A.R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
CMOS integrated circuits;
calibration;
timing circuits;
system-on-chip;
automatic delay calibration method;
multichannel CMOS formatter;
Credence CMOS formatter;
timing generation IC;
internal strobe markers;
independent pin electronics channels;
system on chip;
run time autocalibration circuit;
RIC/DICMOS vernier channels;
prior generation formatters;
independent off-chip signals;
0 to 800 Mbit/s;
21.
Automatic linearity (IP3) test with built-in pattern generator and analyzer
机译:
使用内置码型发生器和分析仪进行自动线性(IP3)测试
作者:
Dai F.
;
Stroud C.
;
Yang D.
;
Shuying Qi
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test pattern generation;
built-in self test;
direct digital synthesis;
integrated circuit testing;
mixed analogue-digital integrated circuits;
analogue integrated circuits;
amplifiers;
field programmable gate arrays;
hardware description languages;
circuit simulation;
automatic linearity test;
built-in pattern generator;
built-in pattern analyzer;
third order intermodulation product;
BIST;
built-in self test;
DDS;
direct digital synthesizer;
analog circuit testing;
mixed signal systems;
amplifier linearity test;
Verilog;
FPGA;
functional testing;
22.
Autonomous yet deterministic test of SOC cores
机译:
SOC核的自主而确定的测试
作者:
Sinanoglu O.
;
Orailoglu A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
integrated circuit testing;
shift registers;
logic gates;
fault diagnosis;
logic testing;
automatic testing;
vectors;
SOC cores;
SOC test;
tester channels;
test vectors;
core scan chains;
tester memory;
core self test;
fault coverage levels;
LFSR;
linear feedback shift register;
pseudo random patterns;
logic gates;
core scan cells;
23.
Benchmarking diagnosis algorithms with a diverse set of IC deformations
机译:
具有多种IC变形的基准诊断算法
作者:
Vogels T.
;
Zanon T.
;
Desineni R.
;
Blanton R.D.
;
Maly W.
;
Brown J.G.
;
Nelson J.E.
;
Fei Y.
;
Huang X.
;
Gopalakrishnan P.
;
Mishra M.
;
Rovner V.
;
Tiwary S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
fault simulation;
integrated circuit testing;
circuit simulation;
benchmark testing;
benchmarking diagnosis algorithms;
IC deformations;
integrated circuits;
logic level models;
IC defect behaviors;
IC diagnosis methodology;
simulation based benchmarking strategy;
circuit level models;
bounded deformations;
24.
BER estimation for serial links based on jitter spectrum and clock recovery characteristics
机译:
基于抖动频谱和时钟恢复特性的串行链路BER估计
作者:
Dongwoo Hong
;
Chee-Kian Ong
;
Kwang-Ting Cheng
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
data communication;
error statistics;
synchronisation;
timing jitter;
production testing;
phase locked loops;
BER estimation;
bit error rate;
serial links;
jitter spectrum characteristics;
clock recovery circuit characteristics;
serial communication systems;
data recovery circuits;
jitter spectral information;
production test time reduction;
phase locked loops;
25.
Built-in self-test for system-on-chip: a case study
机译:
内置的片上系统自检:案例研究
作者:
Stroud C.
;
Sunwoo J.
;
Garimella S.
;
Harris J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
system-on-chip;
field programmable gate arrays;
integrated circuit testing;
integrated circuit design;
logic testing;
application specific integrated circuits;
built-in self test;
system-on-chip;
BIST configurations;
SoC;
field programmable gate array;
application specific logic array;
processor core;
Atmel AT94K series;
programmable logic array;
routing resources;
FPGA configuration memory core;
field programmable system level integrated circuit;
26.
CAEN-BIST: testing the nanofabric
机译:
CAEN-BIST:测试纳米织物
作者:
Brown J.G.
;
Blanton R.D.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
nanoelectronics;
built-in self test;
integrated circuit testing;
fault diagnosis;
field programmable gate arrays;
logic testing;
nanofabrication;
built-in self test algorithm;
field programmable gate arrays;
chemically assembled electronic nanotechnology;
reconfigurability;
fault coverage;
fault diagnostic accuracy;
regular architectures;
high defect densities;
27.
Channel masking synthesis for efficient on-chip test compression
机译:
通道屏蔽综合可实现高效的片上测试压缩
作者:
Chickermane V.
;
Foutz B.
;
Keller B.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
built-in self test;
integrated circuit design;
integrated circuit testing;
automatic test pattern generation;
logic testing;
channel masking synthesis;
on-chip test compression;
product test compression methods;
unknown logic states;
scan elements;
channel masking hardware;
large industrial designs;
typical design flow;
automatic test pattern generation;
28.
Concurrent testing of droplet-based microfluidic systems for multiplexed biomedical assays
机译:
同时进行基于液滴的微流控系统测试,以进行多种生物医学测定
作者:
Su F.
;
Ozev S.
;
Chakrabarty K.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
microfluidics;
biomedical equipment;
built-in self test;
biomolecular electronics;
fault diagnosis;
capacitive sensors;
minimisation;
integer programming;
linear programming;
concurrent testing methodology;
droplet based microfluidic array systems;
multiplexed biomedical assays;
catastrophic fault detection;
test planning;
resource optimization;
multiplexed glucose assays;
multiplexed lactate assays;
integer linear programming model;
testing time minimisation;
droplet dispensing sources;
capacitive sensing circuitry;
bio-MEMS systems;
lab-on-a-chip systems;
biomedical equipment;
biomolecular electronics;
biomedical assays;
reliability;
BIST;
29.
Data compression for multiple scan chains using dictionaries with corrections
机译:
使用带有校正的字典对多个扫描链进行数据压缩
作者:
Wurtenberger A.
;
Tautermann C.S.
;
Hellebrand S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
integrated circuit design;
integrated circuit testing;
automatic test equipment;
data compression;
encoding;
dictionary based compression method;
data compression;
multiple scan chains;
SoC design;
IP cores;
ATE;
onchip decompressor;
encoding;
complex test control;
system under test;
test data serialization;
test vectors;
multiple scan architecture;
30.
Decision selection and learning for an 'all-solutions ATPG engine'
机译:
“全解决方案ATPG引擎”的决策选择和学习
作者:
Chandrasekar K.
;
Hsiao M.S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test pattern generation;
decision making;
sequential circuits;
decision selection heuristics;
all-solutions ATPG engine;
all-solutions ATPG based methods;
model checking sequential circuits;
multiple detect patterns;
success driven learning;
ISCAS89 circuits;
ITC99 circuits;
31.
Delayed-RF based test development for FM transceivers using signature analysis
机译:
使用签名分析的FM收发器基于延迟RF的测试开发
作者:
Acar E.
;
Ozev S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
transceivers;
frequency modulation;
automatic testing;
frequency-domain analysis;
voltage-controlled oscillators;
fault simulation;
digital simulation;
automatic test equipment;
logic testing;
telecommunication equipment testing;
eigenvalues and eigenfunctions;
delayed RF based test development;
FM transceivers;
frequency domain signature analysis;
automatic test development methodology;
delayed RF setup;
eigensignatures;
envelope signatures;
pass/fail criteria;
test generation algorithm;
target fault injection;
fault simulation platform;
VCO modulation;
low IF transceiver architecture;
MATLAB;
behavioral models;
test generation process;
32.
Detecting faults in the peripheral circuits and an evaluation of SRAM tests
机译:
检测外围电路中的故障并评估SRAM测试
作者:
van de Goor Ad.J.
;
Hamdioui S.
;
Wadsworth R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
SRAM chips;
integrated circuit testing;
fault diagnosis;
fault detection;
memory peripheral circuits;
SRAM test;
March test;
March algorithms;
SRAM chips;
512 Kbyte;
0.13 micron;
33.
DFT for test optimisations in a complex mixed-signal SOC - case study on TI's TNETD7300 ADSL modem device
机译:
DFT用于复杂混合信号SOC中的测试优化-以TI TNETD7300 ADSL调制解调器设备为例
作者:
Nikila K.
;
Parekhji R.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
mixed analogue-digital integrated circuits;
integrated circuit design;
system-on-chip;
built-in self test;
integrated circuit testing;
circuit optimisation;
modems;
digital subscriber lines;
silicon;
industrial property;
elemental semiconductors;
DFT;
test optimisations;
complex mixed signal SOC;
TNETD7300 ADSL modem device;
SOC test integration;
SOC test quality;
SOC test cost;
single chip ADSL modem;
analog-digital subsystems;
embedded memories;
analog functions;
clock frequencies;
configurable memory;
BIST operation;
Texas Instruments;
low cost testers;
digital logic functions;
nonhomogeneous IP cores;
SOC test modes;
silicon test;
34.
Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation study
机译:
评估在松弛间隔中检测延迟缺陷的有效性:仿真研究
作者:
Haihua Yan
;
Singh A.D.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
switching circuits;
integrated circuit testing;
fault simulation;
delay defect detection;
delay testing;
slack interval;
neighboring dies;
injected delay faults;
ISCAS benchmark circuits;
RC switching delay model;
delay defect diagnosis;
circuit path delays;
nanometer technology;
fault simulation;
35.
Evaluation of the quality of N-detect scan ATPG patterns on a processor
机译:
在处理器上评估N-detect扫描ATPG模式的质量
作者:
Amyeen M.E.
;
Venkataraman S.
;
Ojha A.
;
Sangbong Lee
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test pattern generation;
microprocessor chips;
fault diagnosis;
test quality evaluation;
N-detect scan ATPG patterns;
Pentium 4 processor;
manufacturing technology;
automatic test pattern generation;
ATPG flow;
bridge fault coverage;
stuck-at fault coverage;
fault detection profile;
90 nm;
36.
Experimental results for high-speed jitter measurement technique
机译:
高速抖动测量技术的实验结果
作者:
Taylor K.
;
Nelson B.
;
Chong A.
;
Nguyen H.
;
Lin H.
;
Soma M.
;
Haggag H.
;
Huard J.
;
Braatz J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
jitter;
high-speed techniques;
BiCMOS integrated circuits;
CMOS integrated circuits;
integrated circuit testing;
integrated circuit design;
high speed jitter measurement technique;
BIST method;
BiCMOS chips;
jitter resolution;
clock signal;
ADC;
external jitter-free reference clock;
30 to 50 ps;
1 GHz;
37.
Fault diagnosis in designs with convolutional compactors
机译:
卷积压实机设计中的故障诊断
作者:
Mrugalski G.
;
Pogiel A.
;
Rajski J.
;
Tyszer J.
;
Chen Wang
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
fault diagnosis;
boundary scan testing;
built-in self test;
integrated circuit testing;
nonadaptive fault diagnosis technique;
convolutional compactors;
scan based designs;
time efficient identification;
failing scan cells;
convolutional test response compaction;
integrated circuit testing;
built-in self test;
38.
Formal description of test specification and ATE architecture for mixed-signal test
机译:
混合信号测试的测试规范和ATE架构的形式描述
作者:
Deng B.
;
Glauert W.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
mixed analogue-digital integrated circuits;
automatic test equipment;
automatic test pattern generation;
matrix algebra;
integrated circuit testing;
formal description;
test specification;
ATE architecture;
mixed signal test;
standard components;
mathematical matrices;
automatic test concept generation;
test program;
device interface board development;
mathematical methods;
39.
Formal verification of a system-on-chip using computation slicing
机译:
使用计算切片对片上系统进行形式验证
作者:
Sen A.
;
Bhadra J.
;
Garg V.K.
;
Abraham J.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
formal verification;
system-on-chip;
peripheral interfaces;
computational complexity;
program slicing;
protocols;
formal verification;
system-on-chip;
computation slicing;
SoC verification;
elegant abstraction mechanism;
execution sequences;
global state space reduction;
polynomial time algorithm;
high level transaction based designs;
MSI cache coherence protocol;
PCI bus;
safety properties;
40.
Hierarchical DFT methodology - a case study
机译:
分层DFT方法论-案例研究
作者:
Remmers J.
;
Villalba M.
;
Fisette R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
design for testability;
integrated circuit design;
integrated circuit testing;
DFT methodology;
SOC designs;
front end design process;
physical design process;
runtime reduction;
pattern size reduction;
additional tester memory;
production design;
sandburst design;
41.
Identifying untestable transition faults in latch based designs with multiple clocks
机译:
识别具有多个时钟的基于锁存器的设计中无法测试的过渡故障
作者:
Syal M.
;
Chakravarty S.
;
Hsiao M.S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
fault diagnosis;
flip-flops;
clocks;
integrated circuit design;
integrated circuit testing;
logic design;
logic testing;
automatic test pattern generation;
sequential circuits;
untestable transition fault identification;
latch based designs;
multiple clock domains;
architectural constraints;
industrial circuits;
state of the art technology;
sequential ATPG tool;
automatic test pattern generation;
functional test development;
stuck-at faults;
42.
IEEE P1500-compliant test wrapper design for hierarchical cores
机译:
符合IEEE P1500的分层核心测试包装设计
作者:
Sehgal A.
;
Goel S.K.
;
Marinissen E.J.
;
Chakrabarty K.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
IEEE standards;
system-on-chip;
integrated circuit design;
integrated circuit testing;
generic IEEE P1500-compliant wrapper architecture;
reconfigurable wrapper design;
hierarchical core wrappers;
benchmark SOC;
system-on-chips;
hierarchical core testing;
embedded cores;
test access mechanism architecture;
single test mode;
wrapper operation;
automatic testing;
heuristic approach;
43.
Implementation of an economic jitter compliance test for a multi-gigabit device on ATE
机译:
在ATE上针对多千兆位设备实施经济抖动合规性测试
作者:
Hansel G.
;
Stieglbauer K.
;
Schulze G.
;
Moreira J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
jitter;
automatic test equipment;
CMOS integrated circuits;
integrated circuit economics;
integrated circuit testing;
production testing;
high-speed integrated circuits;
automatic testing;
transmitters;
time to market;
economic jitter compliance test;
multigigabit device;
ATE system;
communication devices;
multiple high speed interfaces;
SFI4.2 interface;
XAUI interface;
single CMOS chip;
transmitters;
automated test method;
production test;
capital investment;
time to market;
test cost per chip;
jitter separation algorithms;
44.
In search of the optimum test set - adaptive test methods for maximum defect coverage and lowest test cost
机译:
寻找最佳测试集-自适应测试方法,可最大程度地覆盖缺陷并降低测试成本
作者:
Madge R.
;
Benware B.
;
Turakhia R.
;
Daasch R.
;
Schuermyer C.
;
Ruffler J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
silicon;
elemental semiconductors;
integrated circuit testing;
quality control;
cost reduction;
Pareto analysis;
adaptive test methods;
maximum defect coverage;
product quality;
submicron process;
parametric distributions;
vector counts;
binary search routines;
subtle defect screening;
parametric testing;
at-spec testing;
silicon;
test cost reduction;
Pareto analysis;
Si;
45.
Integrating core selection in the SOC test solution design-flow
机译:
将核心选择集成到SOC测试解决方案设计流程中
作者:
Larsson E.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
integrated circuit testing;
integrated circuit design;
core selection integration;
system-on-chip test;
SOC test;
design flow;
design space exploration phase;
core test characteristics;
core test scheduling;
test access mechanism routing;
test set selection;
test resource floor planning;
weighted cost function;
test power limitations;
three level power model;
power grid;
pseudo exhaustive method;
46.
Interconnect delay testings of designs on programmable logic devices
机译:
可编程逻辑器件上设计的互连延迟测试
作者:
Tahoori M.B.
;
Mitra S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
field programmable gate arrays;
delays;
logic testing;
integrated circuit interconnections;
SRAM chips;
fault diagnosis;
interconnect delay testing;
programmable logic devices;
FPGA;
application dependent test;
robust path delay coverage;
transition fault coverage;
TARO coverage;
algorithmic method;
test vectors;
test configurations;
SRAM chips;
fault diagnosis;
47.
Interconnect test pattern generation algorithm for meeting device and global SSO limits with safe initial vectors
机译:
用于满足设备和全局SSO限制以及安全初始向量的互连测试模式生成算法
作者:
Baker K.
;
Nourani M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
boundary scan testing;
integrated circuit testing;
integrated circuit interconnections;
binomial distribution;
automatic test pattern generation;
logic testing;
interconnect test pattern generation algorithm;
safe initial vectors;
switching limit constraints;
true-complement pattern set;
morph vectors reduction;
simultaneous switching output limit;
boundary scan testing;
binomial distribution;
logic testing;
morph vectors elimination;
48.
Logic BIST with scan chain segmentation
机译:
具有扫描链分段的逻辑BIST
作者:
Liyang Lai
;
Patel J.H.
;
Rinderknecht T.
;
Wu-Tung Cheng
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
logic testing;
integrated circuit testing;
automatic test pattern generation;
fault simulation;
logic BIST;
scan chain segmentation;
built-in self test;
pseudo random patterns;
single weight patterns;
circuit under test;
multiple segments;
inverters;
control logic;
49.
Minimizing power consumption in scan testing: pattern generation and DFT techniques
机译:
最小化扫描测试中的功耗:模式生成和DFT技术
作者:
Butler K.M.
;
Saxena J.
;
Jain A.
;
Fryars T.
;
Lewis J.
;
Hetherington G.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
power consumption;
automatic test pattern generation;
design for testability;
low-power electronics;
boundary scan testing;
power consumption minimization;
scan testing;
pattern generation;
DFT techniques;
minimum operating voltages;
at-speed testing;
ATPG;
IC testing;
50.
Modular extension of ATE to 5 Gbps
机译:
ATE的模块化扩展至5 Gbps
作者:
Keezer D.C.
;
Minier D.
;
Paradis M.
;
Binette L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
demultiplexing equipment;
multiplexing equipment;
timing jitter;
calibration;
digital ATE modular extension;
digital automated test equipment;
multiGHz test;
multiplexing channels;
sampling channels;
multiplexers;
demultiplexers;
high speed samplers;
multiple high speed differential signals;
production units;
reclocking techniques;
calibration methods;
timing errors reduction;
system configuration;
jitter;
100 s;
3.2 Gbit/s;
5 Gbit/s;
51.
MRAM defect analysis and fault modeling
机译:
MRAM缺陷分析和故障建模
作者:
Chin-Lung Su
;
Rei-Fu Huang
;
Cheng-Wen Wu
;
Chien-Chung Hung
;
Ming-Jer Kao
;
Yeong-Jar Chang
;
Wen-Ching Wu
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
random-access storage;
integrated memory circuits;
integrated circuit testing;
SPICE;
fault simulation;
integrated circuit modelling;
magnetic random access memory;
memory defect analysis;
memory fault modeling;
embedded memory cores;
onchip memory;
RAM;
EEPROM;
flash memory;
read-write operation;
SPICE model;
stuck-at fault model;
fault simulation;
0.18 micron;
52.
On hazard-free patterns for fine-delay fault testing
机译:
关于用于无延迟故障测试的无危险模式
作者:
Kruseman B.
;
Majhi A.K.
;
Gronthoud G.
;
Eichenberger S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
automatic test pattern generation;
logic testing;
fault simulation;
hazard free patterns;
fine delay fault testing;
defect coverage;
resistive opens;
delay fault patterns;
path length distribution;
delay fault detection;
filtering process;
53.
On random pattern generation with the selfish gene algorithm for testing digital sequential circuits
机译:
利用自私基因算法生成随机模式以测试数字时序电路
作者:
Junwu Zhang
;
Bushnell M.L.
;
Agrawal V.D.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
digital circuits;
sequential circuits;
circuit testing;
automatic test pattern generation;
logic testing;
digital signals;
signal processing;
Hadamard matrices;
random pattern generation;
selfish gene algorithm;
digital sequential circuit testing;
genetic algorithm;
spectral method;
sequential circuit test generation;
Hadamard spectral matrix;
nonlinear digital signal processing;
DSP filtering cutoff values;
vector holding time;
relative input phase shifts;
vector sequences;
fault coverage;
8-bit chunks;
random bit perturbation;
CPU time;
54.
Open architecture test system: system architecture and design
机译:
开放架构测试系统:系统架构与设计
作者:
Rajsuman R.
;
Noriyuki M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
integrated circuit testing;
hardware-software codesign;
open systems;
open architecture test system;
system architecture;
system design;
ATE;
third party instruments;
third party modules;
command communication mechanism;
data communication mechanism;
55.
Production test effectiveness of combined automated inspection and ICT test strategies
机译:
自动化检查和ICT测试策略相结合的生产测试有效性
作者:
Verma A.
;
Robinson C.
;
Butkovich S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
printed circuit testing;
automatic optical inspection;
production testing;
solders;
production test effectiveness;
in-circuit test;
automated inspection systems;
solder joint;
inspection machines;
process indicators;
double sided boards;
production failures;
56.
Quasi-oscillation based test for improved prediction of analog performance parameters
机译:
基于准振荡的测试可改善对模拟性能参数的预测
作者:
Raghunathan A.
;
Chun J.H.
;
Abraham J.A.
;
Chatterjee A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
analogue integrated circuits;
integrated circuit testing;
fault diagnosis;
circuit oscillations;
catastrophe theory;
predictive quasioscillation based technique;
analog performance parameters;
catastrophic fault detect;
parametric fault detection;
CUT;
circuit under test;
process parameter variations;
predictive oscillation based test;
57.
Random and systematic defect analysis using IDDQ signature analysis for understanding fails and guiding test decisions
机译:
使用IDDQ签名分析进行随机和系统的缺陷分析,以了解故障并指导测试决策
作者:
Nigh P.
;
Gattiker A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
failure analysis;
integrated circuit testing;
integrated circuit reliability;
application specific integrated circuits;
signal processing;
random defect analysis;
systematic defect analysis;
IDDQ signature analysis;
reliability defects;
yield detractors;
test decision guidance;
ASIC chips;
signatures classification;
58.
Reducing measurement uncertainty in a DSP-based mixed-signal test environment without increasing test time
机译:
在不增加测试时间的情况下减少基于DSP的混合信号测试环境中的测量不确定度
作者:
Taillefer C.
;
Roberts G.W.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
mixed analogue-digital integrated circuits;
CMOS integrated circuits;
measurement uncertainty;
digital signal processing chips;
timing jitter;
test equipment;
analogue-digital conversion;
measurement uncertainty;
DSP;
mixed signal test environment;
test time;
clock jitter;
mixed signal test system;
high frequency sampling systems;
digitizer architecture;
CMOS process;
measurement accuracy;
59.
Reducing power consumption in memory ECC checkers
机译:
减少内存ECC检查器的功耗
作者:
Ghosh S.
;
Basu S.
;
Touba N.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
error correction codes;
integrated memory circuits;
parity check codes;
minimisation;
power consumption;
Hamming codes;
matrix algebra;
power consumption reduction;
memory ECC checker circuitry;
single error correcting codes;
double error correcting codes;
degrees of freedom;
parity check matrix;
power minimization method;
standard Hamming codes;
odd column weight Hsiao codes;
60.
Routability and fault tolerance of FPGA interconnect architectures
机译:
FPGA互连架构的可路由性和容错能力
作者:
Jing Huang
;
Tahoori M.B.
;
Lombardi F.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
fault tolerance;
field programmable gate arrays;
integrated circuit interconnections;
logic testing;
network routing;
routability;
fault tolerance;
FPGA interconnect architectures;
FPGA routing resources;
interconnect faults;
programmable switches;
wiring channels;
signal routing;
faulty interconnect resources;
probabilistic routing metrics;
61.
Spectral analysis for statistical response compaction during built-in self-testing
机译:
内置自检过程中的频谱分析,用于统计响应压缩
作者:
Omar Khan
;
Bushnell M.L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
logic testing;
spectral analysis;
integrated circuit testing;
fault simulation;
signal processing;
automatic test pattern generation;
spectral analysis;
statistical response compaction;
built-in self test;
spectral BIST system;
digital circuit;
sequential circuits;
spectral test-pattern generator;
spectral response compactors;
multiple input signature register;
automatic test pattern generation;
signal processing;
62.
Speed clustering of integrated circuits
机译:
集成电路的速度聚类
作者:
Brand K.A.
;
Mitra S.
;
Volkerink E.
;
McCluskey E.J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
microprocessor chips;
integrated circuit testing;
design for testability;
dies (machine tools);
speed clustering;
integrated circuits;
test chips;
neighbouring dies;
wafers;
on-chip processor monitors;
cost reduction;
speed binning;
design for testability;
0.18 micron;
63.
SPIN-SIM: logic and fault simulation for speed-independent circuits
机译:
SPIN-SIM:与速度无关的电路的逻辑和故障仿真
作者:
Shi F.
;
Makris Y.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
logic simulation;
fault simulation;
asynchronous circuits;
SPIN-SIM;
logic simulation;
fault simulation;
speed independent circuits;
Eichelberger method;
13-valued algebra;
signal transitions;
pseudo gate equivalents;
fault coverage;
64.
State variable extraction to reduce problem complexity for ATPG and design validation
机译:
状态变量提取可减少ATPG和设计验证的问题复杂性
作者:
Wu Q.
;
Hsiao M.S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test pattern generation;
sequential circuits;
flip-flops;
fault diagnosis;
logic testing;
logic design;
circuit complexity;
state variable extraction;
ATPG;
design validation;
complexity reduction;
flip flops;
characteristic state set;
state correlation information;
state explosion reduction;
very large sequential circuits;
state transition graphs;
test vectors;
stuck at faults;
design errors;
reduced state variables;
65.
Systematic defects in deep sub-micron technologies
机译:
深亚微米技术的系统缺陷
作者:
Kruseman B.
;
Majhi A.
;
Hora C.
;
Eichenberger S.
;
Meirlevede J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
digital circuits;
integrated circuit testing;
integrated circuit yield;
fault diagnosis;
deep submicron technology;
process design interaction;
Moore law;
systematic defect detection;
process development;
test structures;
visual inspection tools;
stuck-at testing;
transition fault testing;
low voltage testing;
manufacturing test;
digital circuits;
integrated circuit yield;
66.
Test programming environment in a modular, open architecture test system
机译:
模块化,开放式架构测试系统中的测试编程环境
作者:
Pramanick A.
;
Krishnaswamy R.
;
Elston M.
;
Adachi T.
;
Harsanjeet Singh
;
Parnas B.
;
Chen L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
semiconductor device testing;
modules;
automatic test equipment;
open systems;
open architecture test system;
device test program development;
modular test system;
test class programming;
pattern management;
software based solutions;
third party hardware modules;
Advantest Corporations T2000 system;
OPENSTAR/spl trade/ specification;
67.
Test scheduling for network-on-chip with BIST and precedence constraints
机译:
具有BIST和优先级约束的片上网络的测试计划
作者:
Chunsheng Liu
;
Cota E.
;
Sharif H.
;
Pradhan D.K.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
integrated circuit testing;
built-in self test;
integer programming;
linear programming;
scheduling;
constraint theory;
BIST test scheduling;
built in self test;
network-on-chip;
precedence constraints;
core based system;
routing path;
NP-complete problems;
ILP model;
integer linear programming model;
heuristics algorithm;
ITC02 SoC benchmarks;
68.
Tester architecture for the source synchronous bus
机译:
源同步总线的测试器架构
作者:
Sivaram A.T.
;
Shimanouchi M.
;
Maassen H.
;
Jackson R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system buses;
logic devices;
logic testing;
automatic test equipment;
protocols;
data communication equipment;
electronic equipment testing;
tester architecture;
source synchronous busses;
digital logic devices;
external system clock;
functional testing;
ATE architectures;
automatic test equipment architecture;
input data signals;
output data signals;
test equipment strobe circuits;
data busses;
high speed communication protocols;
data transfer;
CPU;
peripherals;
high speed bus pins;
69.
Testing high resolution ADCs with low resolution/accuracy deterministic dynamic element matched DACs
机译:
使用低分辨率/精度确定性动态元件匹配DAC测试高分辨率ADC
作者:
Hanjun Jiang
;
Olleta B.
;
Degang Chen
;
Geiger R.L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
mixed analogue-digital integrated circuits;
analogue-digital conversion;
digital-analogue conversion;
ramp generators;
built-in self test;
integrated circuit testing;
production testing;
ADC testing;
DAC;
deterministic dynamic element matching;
stimulus signals generation;
on-chip linear ramp generators;
production test;
BIST environments;
built-in-self-test;
70.
Testing micropipelined asynchronous circuits
机译:
测试微管线异步电路
作者:
King M.L.
;
Saluja K.K.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
asynchronous circuits;
finite state machines;
fault diagnosis;
design for testability;
micropipelined asynchronous circuits;
asynchronous circuit testing;
design for testability;
asynchronous elements;
C-element;
atomic state elements;
finite state machines;
hardware reduction;
micropipeline testing methods;
asynchronous circuit design;
71.
Testing the configurable analog blocks of field programmable analog arrays
机译:
测试现场可编程模拟阵列的可配置模拟模块
作者:
Balen T.
;
Andrade A. Jr.
;
Azais F.
;
Lubaszewski M.
;
Renovell M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
field programmable analogue arrays;
built-in self test;
logic testing;
fault diagnosis;
switching circuits;
capacitors;
configurable analog block switches;
FPAA;
field programmable analog arrays;
programmable capacitors;
programmable gains;
input amplifiers;
stuck on faults;
stuck open faults;
test stimuli generation;
oscillation test strategy;
test response analysis;
BIST;
built-in self-test;
output response analyzer;
Lattice Semiconductor Corporation;
fault coverage;
test application time;
external hardware resources;
72.
Timing accuracy enhancement by a new calibration scheme for multi-Gbps ATE
机译:
通过针对多Gbps ATE的新校准方案增强了时序精度
作者:
Shimanouchi M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
calibration;
timing jitter;
automatic test equipment;
timing circuits;
test timing accuracy enhancement;
multiGbps ATE;
high speed I/Os;
timing calibration methods;
timing error mechanism;
data dependent jitter;
device under test;
pin to pin skew;
73.
Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault models
机译:
使用替代故障模型在延迟产生缺陷的情况下对串扰进行与时序无关的测试
作者:
Irajpour S.
;
Gupta S.K.
;
Breuer M.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
crosstalk;
delays;
fault diagnosis;
combinational circuits;
automatic test pattern generation;
timing independent crosstalk testing;
delay producing defects;
surrogate fault models;
crosstalk slowdown test generation;
gate delays;
wire delays;
timing independent conditions;
pin-to-pin delay model;
two vector sequences;
combinational circuits;
ISCAS 89 circuits;
74.
Transfer functions for the reference clock jitter in a serial link: theory and applications
机译:
串行链路中参考时钟抖动的传递函数:理论与应用
作者:
Mike Li
;
Martwick A.
;
Talbot G.
;
Wilstrup J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
timing jitter;
transfer functions;
synchronisation;
data communication;
phase locked loops;
error statistics;
numerical analysis;
jitter transfer functions;
reference clock jitter;
serial link;
PCI express link system;
clock circuits;
data recovery circuits;
mathematical interrelationships;
phase jitter;
period jitter;
cycle to cycle jitter;
BER;
bit error rate;
clock testing;
numerical simulations;
receiver;
phase locked loop;
100 MHz;
75.
Trends in testing integrated circuits
机译:
测试集成电路的趋势
作者:
Vermeulen B.
;
Hora C.
;
Kruseman B.
;
Marinissen E.J.
;
van Rijsinge R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
design for testability;
integrated circuit technology;
electronics industry;
automatic test equipment;
integrated circuit testing;
integrated circuit process technology;
design complexity;
customer quality requirements;
test quality;
test program development;
Philips;
electronics industry;
design for testability;
automatic test equipment;
76.
Tri-scan: a novel DFT technique for CMOS path delay fault testing
机译:
Tri-scan:用于CMOS路径延迟故障测试的新颖DFT技术
作者:
Datta R.
;
Ravi Gupta
;
Sebastine A.
;
Abraham J.A.
;
dAbreu M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
CMOS integrated circuits;
design for testability;
VLSI;
fault simulation;
integrated circuit testing;
integrated circuit design;
combinational circuits;
sequential circuits;
tri-scan scheme;
DFT technique;
design for testability;
CMOS path delay fault testing;
deep submicron VLSI chips;
stuck-at fault detection;
scan-shifting technique;
scan based designs;
combinational logic;
power reduction;
sequential circuits;
77.
VirtualScan: a new compressed scan technology for test cost reduction
机译:
VirtualScan:一种新的压缩扫描技术,可降低测试成本
作者:
Wang L.-T.
;
Xiaoqing Wen
;
Furukawa H.
;
Fei-Sheng Hsu
;
Shyh-Horng Lin
;
Sen-Wei Tsai
;
Abdel-Hafez K.S.
;
Shianling Wu
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test pattern generation;
cost reduction;
integrated circuit design;
integrated circuit testing;
virtual reality;
VirtualScan technology;
scan test cost reduction;
VirtualScan circuit;
external scan ports;
internal scan chains;
broadcaster;
compactor;
VirtualScan ATPG;
multicapture clocking;
industrial chips;
78.
X-masking during logic BIST and its impact on defect coverage
机译:
逻辑BIST期间的X遮罩及其对缺陷覆盖率的影响
作者:
Yuyi Tang
;
Wunderlich H.-J.
;
Vranken H.
;
Hapke F.
;
Wittke M.
;
Engelke P.
;
Polian I.
;
Becker B.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
logic testing;
probability;
X-masking;
logic BIST;
defect coverage;
output response;
stuck-at n-detection based metric;
probabilistic model;
resistive short defects;
79.
X-tolerant signature analysis
机译:
耐X签名分析
作者:
Mitra S.
;
Lumetta S.S.
;
Mitzenmacher M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
logic testing;
built-in self test;
data compression;
logic analysers;
stochastic processes;
encoding;
X-tolerant signature analysis;
stochastic coding;
defective chip detection;
signature analyzer design;
built-in self-test;
data compression;
industrial designs;
80.
A hierarchical DFT architecture for chip, board and system test/debug
机译:
用于芯片,电路板和系统测试/调试的分层DFT体系结构
作者:
Njinda C.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
reconfigurable architectures;
integrated circuit testing;
system-on-chip;
IEEE standards;
network routing;
hierarchical DFT architecture;
chip test;
chip debug;
board test;
board debug;
system test;
system debug;
Procket DFT architecture;
manufacturability;
on-chip DFT structures;
reconfigurable scan chains;
IEEE 1149.1 ports;
81.
The leading edge of production wafer probe test technology
机译:
生产晶圆探针测试技术的领先优势
作者:
Mann W.R.
;
Taber F.L.
;
Seitzer P.W.
;
Broz J.J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
integrated circuit manufacture;
production testing;
integrated circuit design;
leading edge characteristics;
microelectronic wafer testing;
die level testing;
minimum I/O pad pitch;
wafer frequency testing;
probe contactor cleaning;
I/O pad damage minimization;
communication methods;
I/O pad designs;
production wafer probe test;
82.
ITC Technical Paper Evaluation and Selection Process
机译:
ITC技术论文评估和选择过程
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
83.
International Test Conference 2005 - Call for Papers
机译:
2005年国际考试大会-征文通知
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
84.
Test in the era of 'What you see is not what you get' - Keynote address
机译:
在“所见即所得”时代进行测试-主题演讲
作者:
Koenemann B.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
85.
New test paradigms for yield and manufacturability - Invited address
机译:
成品率和可制造性的新测试范例-邀请的地址
作者:
Madge R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
86.
Proceedings International Test Conference 2004 - Title Page
机译:
2004年国际会议论文集-标题页
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
87.
Copyright
机译:
版权
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
88.
Welcome Message
机译:
欢迎留言
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
89.
In Memoriam Nathaniel 'Ned' Kornfield
机译:
在纪念Nathaniel“ Ned” Kornfield
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
90.
ITC 2003 Paper Awards
机译:
ITC 2003论文奖
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
91.
International Test Conference 2004 - Technical Program Committee
机译:
2004年国际测试大会-技术计划委员会
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
92.
Blank Page
机译:
空白页
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
93.
Blank Page
机译:
空白页
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
94.
Back Cover Page
机译:
封底
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
95.
Blank Page
机译:
空白页
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
96.
International Test Conference 2004 - Steering Committee and Subcommittees
机译:
2004年国际测试会议-指导委员会和小组委员会
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
97.
TTTC: Test Technology Technical Council
机译:
TTTC:测试技术委员会
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
98.
ITC 2004 - Technical Program Committee
机译:
ITC 2004-技术计划委员会
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
99.
Author Index
机译:
作者索引
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
100.
International Test Conference - 2004 Technical Paper Reviewers
机译:
国际测试会议-2004年技术论文审稿人
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
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