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IEEE Custom Integrated Circuits Conference
IEEE Custom Integrated Circuits Conference
召开年:
2015
召开地:
San Jose, CA(US)
出版时间:
-
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1.
Session 2 — Low power analog
机译:
第2节-低功耗模拟
作者:
Naraghi Shahrzad
;
Piovaccari Alessandro
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
analogue integrated circuits;
low-power electronics;
analog circuits;
low power analog;
scaled technology;
ultra-low power circuits;
Analog circuits;
Laboratories;
Low-power electronics;
Oscillators;
Silicon;
Temperature measurement;
Temperature sensors;
2.
Session 20 — Manufacturing beyond moore's law
机译:
第二十讲-超越摩尔定律的制造
作者:
Jansen Philippe
;
Venkatraman Ramnath
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
manufacturing processes;
Moore law;
manufacturing process;
Computer architecture;
Gallium nitride;
Manufacturing processes;
Silicon;
Strain;
Three-dimensional displays;
3.
Session 22 — High frequency analog techniques
机译:
第二十二节—高频模拟技术
作者:
Hancock Timothy M.
;
Grilo Jorge
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue processing circuits;
band-pass filters;
gallium compounds;
high electron mobility transistors;
low-pass filters;
phase locked loops;
3suprd/sup-order filter;
BiCMOS process;
CMOS process;
GaN;
HEMT process;
ILFD;
MOS varactors;
RF systems;
Schottky contact gate;
SiGe;
T/H applications;
capacitors;
data acquisition systems;
distortion cancellation techniques;
dual varactor;
filter resistors;
frequency 2.25 GHz to 4.5 GHz;
frequency 34 MHz to 314 MHz;
gate leakage;
high SNR track-and-hold;
high frequency analog techniques;
independent Q-tuning;
injection locked PLL;
injection locked frequency divider;
inverter-based gsubm/sub-cells;
low power calibration;
negative feedback circuits;
nonlinear MOSCAPs;
oscillator;
phase shift;
power 3.74 mW;
power 4.6 mW;
size 0.13 mum;
size 0.25 mum;
size 65 nm;
tunable RF bandpass filter;
tunable delay line;
tunable low-pass filter;
varactor 3rd order distortion;
voltage 0.9 V;
4.
Session 23 — Modeling emerging devices
机译:
第23节-新兴设备建模
作者:
Chenjie Gu
;
Onodera Hidetoshi
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
integrated circuit modelling;
statistical analysis;
CMOS devices;
bioelectronics;
device variability;
energy harvesting;
mobile computing;
statistical techniques;
variability analysis techniques;
wearable computing;
Biological system modeling;
CMOS integrated circuits;
Computational modeling;
Energy harvesting;
Integrated circuit modeling;
Numerical models;
Semiconductor device modeling;
5.
Session 25 — 20 Gb/s transmitters and receivers
机译:
第25节-20 Gb / s发射机和接收机
作者:
Jun Cao
;
Mirabbasi Shahriar
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS logic circuits;
driver circuits;
equalisers;
integrated optoelectronics;
optical crosstalk;
optical delay lines;
optical transceivers;
surface emitting lasers;
2-tap FFE;
CMOS logic-style circuits;
SOI CMOS process;
VCSEL transmitter;
bit rate 25 Gbit/s to 20 Gbit/s;
clock path;
current-dependent dynamic RLC model;
electrical receivers;
electrical transmitters;
far-end crosstalk cancellation technique;
half-rate clock;
loss 12.9 dB;
low bias current;
low-power optical receivers;
low-power optical transmitters;
low-power transceiver;
nonlinear equalization;
passive equalizers;
power efficiency;
predriver;
quarter-rated clock;
signal degradation;
single-ended signaling;
size 28 nm;
size 32 nm;
size 65 nm;
voltage controlled delay line;
voltage-mode driver;
Bandwidth;
CMOS process;
Clocks;
Optical transmitters;
Receivers;
Transceivers;
Vertical cavity surface emitting lasers;
6.
Session 3 — Optical interconnect and reliability enhancement techniques
机译:
第3节-光互连和可靠性增强技术
作者:
Iizuka Tetsuya
;
Yamaguchi Takahiro
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS logic circuits;
flip-flops;
integrated circuit reliability;
optical interconnections;
semiconductor lasers;
system-on-chip;
voltage control;
CMOS technology;
SoC design flow;
bias temperature instability;
device aging;
electrical concurrent design methodology;
flip-flops;
laser diodes;
optical concurrent design methodology;
optical interconnect design optimization;
random jitter reduction;
reliability enhancement techniques;
successive approximation register;
supply voltage scaling;
threshold voltage instability;
voltage regulation;
Monitoring;
Optical interconnections;
Optical transmitters;
Reliability;
Temperature measurement;
Temperature sensors;
Timing;
7.
Session 4 — Frequency and phase generation techniques
机译:
第4节-频率和相位产生技术
作者:
Dai Fa Foster
;
Sankaran Swaminathan
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
Couplers;
Frequency modulation;
Hybrid power systems;
Interpolation;
Tuning;
8.
Session 6 — Analog circuits using digital cells
机译:
第6节—使用数字单元的模拟电路
作者:
Jing Yang
;
Raychowdhury Arijit
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue integrated circuits;
hardware description languages;
invertors;
operational amplifiers;
time-digital conversion;
CMOS integrated circuit;
Verilog code;
analog biquad filter;
analog circuits;
bandwidth 1.7 MHz to 2.5 MHz;
cell library elements;
digital cells;
digital switched ring oscillator;
inverter based OTA;
inverter based amplifier cells;
power 0.8 mW;
power 2 mW;
programmable gain;
reconfigurable multistate op-amp;
size 0.13 mum;
size 65 nm;
state-of-the-art techniques;
time amplifier;
two-step time-to-digital converter;
voltage 0.4 V;
voltage 1 V;
word length 8 bit;
Analog circuits;
CMOS integrated circuits;
Filtering theory;
Inverters;
Libraries;
Oscillators;
Switching circuits;
9.
Session 7 — Advances in biomedial sensor systems
机译:
第7节-生物医学传感器系统的进展
作者:
Antoine Christophe
;
Muller Rikky
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
biomedical electronics;
biosensors;
medical signal processing;
CMOS ISFET sensor;
biomedial sensor systems;
compressed-sensing;
high rate data communication;
implantable devices;
passive rectifier;
power management;
signal processing technique;
signal reconstruction;
voltage doubling rectifier;
voltage doubling regulator;
voltage regulation transistor;
wireless transceiver;
Biosensors;
CMOS integrated circuits;
CMOS technology;
Implants;
Rectifiers;
Signal processing;
Voltage control;
10.
Session 9 — Advanced simulation techniques
机译:
第9节-先进的模拟技术
作者:
McAndrew Colin
;
Nagel Larry
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
impedance matching;
integrated circuit modelling;
advanced simulation techniques;
behavioral modeling techniques;
impedance matching networks;
integrated circuits;
lossy passive elements;
modeling framework;
Adaptation models;
Baseband;
Impedance matching;
Integrated circuit modeling;
Mathematical model;
Phase locked loops;
11.
Session 11 — Advanced techniques for power amplifier transceiver front-ends
机译:
第11节—功率放大器收发器前端的先进技术
作者:
Yanjie Wang
;
Hua Wang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
millimetre wave power amplifiers;
radio transceivers;
wideband amplifiers;
broadband mm-wave linear power amplifier;
dual-band linear digital polar power amplifier;
mm-wave switching power amplifier;
power amplifier transceiver front-end;
Dual band;
Harmonic analysis;
Impedance matching;
Power amplifiers;
Power generation;
Power harmonic filters;
Transceivers;
12.
Session 12 — Tutorial — beyond CMOS: Large area electronics-concepts and prospects
机译:
第十二部分—教程—超越CMOS:大面积电子学的概念和前景
作者:
Aitken Robert
;
Iizuka Tetsuya
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
flexible electronics;
organic field effect transistors;
radiofrequency identification;
thin film transistors;
CMOS semiconductor;
bio-array sensors;
large area electronics;
large-area flexible sensors;
large-area flexible substrates;
low-cost RFID tags;
organic field-effect transistors;
thin film field-effect transistors;
CMOS integrated circuits;
Performance evaluation;
Substrates;
Thermal stability;
Thin film transistors;
Tutorials;
13.
Session 18 — Data converter techniques
机译:
第十八节—数据转换器技术
作者:
McNeill John
;
Bandyopadhyay Abhishek
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
analogue-digital conversion;
VCO-based ADC;
data converter techniques;
folding ADC;
non-uniform sampling ADC;
successive approximation ADC;
time-interleaved ADC;
Approximation methods;
CMOS integrated circuits;
Energy efficiency;
Market research;
Performance evaluation;
Time-domain analysis;
14.
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing
机译:
一个全功能的90nm 8Mb STT MRAM演示器,具有基于参考单元的修整信号
作者:
DeBrosse John
;
Maffitt Thomas
;
Nakamura Yutaka
;
Jan Guenole
;
Po-Kang Wang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
MRAM devices;
reference circuits;
STT MRAM demonstrator;
reference cell-based sensing;
size 90 nm;
spin transfer torque magnetoresistive RAM;
Arrays;
Error correction codes;
Field effect transistors;
Magnetic tunneling;
Microprocessors;
Random access memory;
ECC;
MRAM;
STT;
sense;
write;
15.
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology
机译:
ASIC SOC中的自定义6 R,2或4 W多端口寄存器文件,采用28 nm HKMG CMOS技术的DVFS窗口为0.5 V,130 MHz至0.96 V,3.2 GHz
作者:
Hsieh Henry
;
Dhong Sang H.
;
Cheng-Chung Lin
;
Ming-Zhang Kuo
;
Kuo-Feng Tseng
;
Ping-Lin Yang
;
Kevin Huang
;
Min-Jer Wang
;
Wei Hwang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
microwave integrated circuits;
system-on-chip;
ASIC SOC;
DVFS window;
GRF;
HKMG CMOS technology;
bypass control block;
frequency 130 MHz;
frequency 3.2 GHz;
general-purpose register file;
logic synthesized version;
multiport register file;
power 2 W;
power 4 W;
size 28 nm;
voltage 0.5 V;
voltage 0.96 V;
CMOS integrated circuits;
Latches;
Registers;
System-on-chip;
Transistors;
Wiring;
ASIC;
DVFS;
Register files;
SOC;
multi-port;
16.
A 2.2 GS/s 188mW spectrometer processor in 65nm CMOS for supporting low-power THz planetary instruments
机译:
采用65nm CMOS的2.2 GS / s 188mW光谱仪处理器,可支持低功率THz行星仪器
作者:
Hsiao F.
;
Tang A.
;
Kim Y.
;
Drouin Brian
;
Chattopadhyay Goutam
;
Chang M.-C Frank
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
low-power electronics;
space vehicle electronics;
spectrometers;
terahertz spectroscopy;
512 point PSD processor;
512-channel spectrometer processor;
ADC IQ converters;
NASA planetary missions;
averaging accumulator;
band RF front-end receiver;
bandwidth 1.1 GHz;
low-power THz planetary instruments;
power 188 mW;
power consumption;
solar system;
trace gases detection;
word length 7 bit;
Atmospheric measurements;
CMOS integrated circuits;
Computer architecture;
Instruments;
NASA;
Receivers;
Space vehicles;
17.
Supply noise induced jitter modeling and optimization for high-speed interfaces
机译:
电源噪声引起的高速接口抖动建模和优化
作者:
Dan Oh
;
Yujeong Shim
;
Guang Chen
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
circuit optimisation;
integrated circuit design;
integrated circuit interconnections;
integrated circuit noise;
interference;
jitter;
system buses;
timing;
digital logic timing;
high speed interface optimization;
memory bus interface;
parallel bus interface;
power distribution network;
power supply induced jitter;
serial links;
supply noise induced jitter modeling;
18.
Resonant wireless power transfer technology integration roadmap
机译:
谐振无线功率传输技术和集成路线图
作者:
Carobolante Francesco
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
Bluetooth;
inductive power transmission;
magnetic resonance;
mobile antennas;
radiofrequency amplifiers;
rectifiers;
smart phones;
system-in-package;
BLE;
Bluetooth low energy;
RF amplifier;
RF exposure estimation;
SmartWatch;
dual-port matched filter;
full wave rectifiers;
half wave rectifiers;
magnetic coupling;
magnetic induction;
magnetic resonance;
mobile antenna;
power receiving unit;
power transmitting unit;
receiver architecture;
resonant wireless power transfer technology;
smartphones;
system-in-package;
transmitter resonator;
wireless charging;
Inductive charging;
Magnetic resonance;
Market research;
Standardization;
Wireless communication;
19.
Low dropout regulators
机译:
低压差稳压器
作者:
Hanumolu Pavan Kumar
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
controllers;
load regulation;
transient response;
voltage regulators;
low dropout regulators;
DC-DC power converters;
Regulators;
Voltage control;
20.
Phase-locked frequency synthesis and modulation for modern wireless transceivers
机译:
现代无线收发器的锁相频率合成和调制
作者:
Woogeun Rhee
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
modulation;
network synthesis;
phase locked loops;
radio transceivers;
time-digital conversion;
DPLL;
PLL architectures;
PLL system design;
TDC;
circuit design;
circuit techniques;
fractional-N PLL;
phase-locked frequency synthesis;
time-digital conversion;
wireless transceivers;
Frequency modulation;
Frequency synthesizers;
Phase locked loops;
Phase modulation;
Synthesizers;
Transceivers;
Tutorials;
21.
Multiphase RF techniques in CMOS: Applied to beam‐forming and full duplex receivers: CICC 2015 educational session
机译:
CMOS中的多相RF技术:应用于波束成形和全双工接收器:CICC 2015教育会议
作者:
Nauta Bram
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
Q-factor;
antenna radiation patterns;
array signal processing;
frequency response;
radio receivers;
radiofrequency interference;
spatial filters;
CICC 2015 educational session;
CMOS integrated circuit;
N path filters;
antenna pattern;
antenna spacing;
basic N-path topology;
beamforming;
differential version;
frequency response;
full duplex receivers;
interference;
large RC time constant;
low pass-bandpass transformation;
multiphase RF techniques;
quality factor;
signal-to-noise ratio;
spatial filtering;
Array signal processing;
22.
MAA evolution: Common access/backhaul reference platform
机译:
MAA演进:通用接入/回程参考平台
作者:
Sadri Ali
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
5G mobile communication;
MIMO communication;
array signal processing;
millimetre wave antenna arrays;
multi-access systems;
radio links;
5G communication;
MAA evolution;
MIMO communication;
antenna beam steering;
backhaul reference platform;
common access platform;
link budget calculation;
millimeter wave system beamforming;
modular antenna array;
multiple access communication;
5G mobile communication;
Buildings;
IEEE 802.11 Standard;
Licenses;
Resource management;
Throughput;
23.
SAR ADCs in parallel time-interleaved converter arrays
机译:
并行时间交错转换器阵列中的SAR ADC
作者:
Kapusta Ron
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
convertors;
CMOS process;
SAR ADC;
high-performance interleaved systems;
high-speed interleaved systems;
parallel converter arrays;
24.
A few behavioral modeling options for balancing verification coverage and credibility
机译:
一些行为建模选项,可平衡验证范围和可信度
作者:
Chen Jess
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
electronic engineering computing;
formal verification;
integrated circuit modelling;
behavioral modeling option;
classical modeling;
high-level flat model;
model credibility;
modeling strategy;
silicon risk reduction;
test coverage;
transistor-level model;
unmodeled circuit bugs;
verification coverage;
Calculators;
Force;
Logic gates;
Schedules;
Semiconductor device modeling;
Transistors;
25.
A millimeter-wave fully differential transformer-based passive reflective-type phase shifter
机译:
基于毫米波全差动变压器的无源反射型移相器
作者:
Tso-Wei Li
;
Hua Wang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
BiCMOS integrated circuits;
differential transformers;
millimetre wave couplers;
phase shifters;
BiCMOS process;
FoM;
RTPS design;
figure-of-merit;
frequency 58 GHz to 64 GHz;
frequency 62 GHz;
millimeterwave fully differential compact transformer;
multiresonance reflective loads;
passive reflective-type phase shifter;
phase shifting;
size 130 nm;
size 340 mum;
size 480 mum;
Arrays;
BiCMOS integrated circuits;
Couplers;
Frequency measurement;
Insertion loss;
Phase transformers;
Beam-forming;
beam-steering;
millimeter-wave;
phased array;
reflective-type phase shifter;
26.
A mixed-domain modeling method for RF systems
机译:
射频系统的混合域建模方法
作者:
Zhimiao Chen
;
Zhixing Liu
;
Lei Liao
;
Wunderlich Ralf
;
Heinen Stefan
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
frequency-domain analysis;
integrated circuit modelling;
mixed analogue-digital integrated circuits;
radiofrequency integrated circuits;
time-domain analysis;
RF systems;
baseband modeling methods;
circuit behaviors;
equivalent baseband representation;
harmonic balance simulation techniques;
mixed domain event-driven modeling method;
mixed-signal circuit modeling;
passband signal abstraction;
spectral component;
time-frequency domain;
Accuracy;
Baseband;
Frequency-domain analysis;
Integrated circuit modeling;
Phase locked loops;
Radio frequency;
Time-domain analysis;
27.
A linear transconductance amplifier with differential-mode bandwidth extension and common-mode compensation
机译:
具有差模带宽扩展和共模补偿的线性跨导放大器
作者:
Derui Kong
;
Sang Min Lee
;
Taleie Shahin Mehdizad
;
McGowan Michael Joseph
;
Dongwon Seo
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS analogue integrated circuits;
circuit stability;
distortion;
operational amplifiers;
CMOS process;
DACs;
common-mode positive capacitance;
common-mode stability compensation;
differential-mode bandwidth extension;
differential-mode negative capacitance;
distortion performance;
filters;
linear transconductance amplifier;
negative transconductance circuit;
size 20 nm;
Bandwidth;
Capacitance;
Distortion;
Frequency response;
Impedance;
Transconductance;
Tuning;
CMOS;
DAC;
R-2R;
negative capacitance;
negative resistance;
transconductance;
28.
A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS
机译:
28 nm CMOS中基于低能量SRAM的物理不可克隆的函数基元
作者:
Neale Adam
;
Sachdev Manoj
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS memory circuits;
SRAM chips;
data integrity;
error correction;
low-power electronics;
data integrity masking;
design-time cell asymmetry metric;
error correction parity-bit overhead;
low energy SRAM-based physically unclonable function;
multi-bit error correcting circuit;
size 28 nm;
static noise margin difference;
voltage 0.6 V to 1 V;
Arrays;
Error analysis;
Error correction;
SRAM cells;
Semiconductor device measurement;
29.
A power electronics unit to drive piezoelectric actuators for flying microrobots
机译:
电力电子单元,用于驱动微型机器人的压电致动器
作者:
Lok Mario
;
Xuan Zhang
;
Helbling Elizabeth Farrell
;
Wood Robert
;
Brooks David
;
Gu-Yeon Wei
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
aerospace robotics;
driver circuits;
energy conservation;
microrobots;
piezoelectric actuators;
power consumption;
power electronics;
PEU;
actuator driver IC;
capacitance 15 nF;
capacitor load;
charge sharing;
dynamic common mode;
envelope tracking;
flying microrobot;
inductorless linear driver;
insect-scale flapping-wing robot;
piezoelectric actuator;
power 290 mW;
power consumption reduction;
power electronics unit;
power saving technique;
Capacitors;
Piezoelectric actuators;
Power demand;
Power electronics;
Robots;
Topology;
BCD;
capacitive loads;
high voltage driver;
microrobot;
piezoelectric actuator driver;
30.
A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation
机译:
具有功耗和面积效率的10×10 Gb / s自举收发器,采用40 nm CMOS,可实现无参考和与通道无关的操作
作者:
Joon-Yeong Lee
;
Kwangseok Han
;
Taeho Kim
;
Sang-Eun Lee
;
Jeong-Sup Lee
;
Taehun Yoon
;
Jinho Park
;
Hyeon-Min Bae
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
flip-chip devices;
transceivers;
voltage-controlled oscillators;
CMOS technology;
OC-192 jitter-tolerance specification;
PI output clock signals;
VCO frequency locking;
VCO-based parallel reference-less designs;
bit rate 10 Gbit/s;
flip-chip packaged test chip;
lane-independent operation;
phase interpolator;
power-and-area efficient bootstrap transceiver;
receiver figure-of-merits;
recovered-data jitter;
size 40 nm;
transmitter figure-of-merits;
voltage-controlled oscillator;
Reference-less and lane-independent clock and data recovery (CDR);
bootstrap;
parallel transceiver;
phase interpolator-based CDR;
31.
A field-programmable noise-canceling wideband receiver with high-linearity hybrid class-AB-C LNTAs
机译:
具有高线性度混合型AB-C LNTAs的现场可编程降噪宽带接收机
作者:
Jianxun Zhu
;
Kinget Peter R.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
MMIC;
radio receivers;
LP CMOS receiver;
antenna port;
common-gate LNTA;
common-source LNTA;
current 15 mA to 40 mA;
current 2.2 mA to 20 mA;
field-programmable noise-canceling wide-band receiver front end;
field-programmable noise-canceling wideband receiver;
gain 53 dB;
high-linearity hybrid class-AB-C LNTA;
noise figure 2.2 dB;
size 40 nm;
voltage 1.1 V;
voltage 2.5 V;
Frequency measurement;
Linearity;
MOS devices;
Mixers;
Noise measurement;
Receivers;
Wideband;
32.
A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer
机译:
硅中介层上的可扩展和可重新配置的2.5D集成多核处理器
作者:
Jie Lin
;
Shikai Zhu
;
Zhiyi Yu
;
Dongjun Xu
;
Sai Manoj P. D.
;
Hao Yu
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
elemental semiconductors;
integrated circuit interconnections;
microprocessor chips;
silicon;
telecommunication channels;
2.5D integrated multicore processor;
8 MIPS-cores;
SRAM die;
SerDes;
Si;
accelerator die;
communication applications;
core-accelerator;
core-core;
core-memory;
frequency 500 MHz;
interdie communication channels;
multimedia applications;
power 1.08 W;
processor die;
silicon interposer;
size 65 nm;
voltage 1.2 V;
Bandwidth;
Clocks;
Decoding;
Memory management;
Metals;
Multicore processing;
System-on-chip;
2.5D stacking;
SerDes;
TSI;
high bandwidth;
multicore processor;
through-silicon interposer;
33.
A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS
机译:
具有32nm SOI CMOS非线性均衡功能的20Gb / s 0.77pJ / b VCSEL发送器
作者:
Raj Mayank
;
Monge Manuel
;
Emami Azita
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
optical transmitters;
silicon-on-insulator;
surface emitting lasers;
CMOS;
SOI;
VCSEL transmitter;
bit rate 20 Gbit/s;
nonlinear equalization;
power efficiency;
size 32 nm;
Decision support systems;
equalization;
nonlinear;
optical;
transmitter;
vertical-cavity surface-emitting laser (VCSEL);
34.
A soft-error hardened process portable embedded microprocessor
机译:
一种软错误强化的过程便携式嵌入式微处理器
作者:
Vashishtha Vinay
;
Clark Lawrence T.
;
Chellappa Srivatsan
;
Gogulamudi Anudeep R.
;
Gujja Aditya
;
Farnsworth Chad
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS logic circuits;
flip-flops;
microprocessor chips;
radiation hardening (electronics);
bulk CMOS process;
dual-redundant speculative pipeline;
error correction;
full clock gating;
nearthreshold low voltage operation;
register file based cache;
size 90 nm;
soft-error hardened process portable embedded microprocessor core;
software controlled recovery;
triple-mode redundant self-correcting logic;
Clocks;
Pipelines;
Radio frequency;
Registers;
Silicon;
Standards;
Tunneling magnetoresistance;
Radiation hardening;
microprocessor architecture;
single event effects;
soft-errors;
35.
A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS
机译:
具有90nm CMOS的单个LC VCO的DC至12.5Gb / s 4.88mW / Gb / s全速率CDR
作者:
Jong-Hyeok Yoon
;
Soon-Won Kwon
;
Hyeon-Min Bae
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
LC circuits;
clock and data recovery circuits;
dividing circuits;
error statistics;
filters;
gain control;
integrated circuit testing;
voltage-controlled oscillators;
CMOS;
CTLE;
all-rate CDR IC;
all-rate clock signals;
asynchronous phase calibration scheme;
automatic loop gain control scheme;
channel loss;
one-tap DFE;
optimum BER performance;
power efficiency;
single LC VCO;
size 90 nm;
static fractional dividers;
test chip;
three-tap preemphasis filter;
Bit error rate;
Calibration;
Clocks;
Frequency conversion;
Generators;
Jitter;
Voltage-controlled oscillators;
All-rate CDR;
asynchronous calibration loop;
automatic loop gain calibration;
static fractional divider;
36.
An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier
机译:
采用基于开关环形振荡器的时间放大器的65nm CMOS器件中的8位,2.6ps两步TDC
作者:
Bongjin Kim
;
Hoonki Kim
;
Kim Chris H.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS digital integrated circuits;
amplifiers;
logic design;
oscillators;
switched networks;
time-digital conversion;
CMOS;
TA gain;
digital switched ring-oscillator;
power 2 mW;
programmable gain;
size 0.07 mm;
size 65 nm;
time amplifier;
two-step TDC;
two-step time-to-digital converter;
CMOS integrated circuits;
Calibration;
Delay lines;
Delays;
Logic gates;
Switches;
Switching circuits;
37.
A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants
机译:
适用于大电流生物医学植入物的接近最佳的13.56 MHz有源整流器,具有电路延迟实时校准
作者:
Cheng Huang
;
Kawajiri Toru
;
Ishikuro Hiroki
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
MOSFET;
biomedical electronics;
calibration;
compensation;
prosthetics;
rectifiers;
AS;
PCE;
TSMC;
VCR;
adaptive sizing;
circuit-delay real-time calibration;
compensation;
efficiency 94.8 percent;
frequency 13.56 MHz;
high-current biomedical implant;
near-optimum active rectifier;
power 248.1 mW;
power conversion efficiency;
real-time NMOS on-off calibration;
resistance 1 kohm;
resistance 80 ohm;
reverse current minimization;
size 65 nm;
transistor conduction time maximization;
voltage 2.5 V;
voltage conversion ratio;
Decision support systems;
Active rectifier;
adaptive sizing;
biomedical implants;
circuit delays;
conduction time;
power conversion efficiency;
real-time calibrations;
reverse current;
voltage conversion ratio;
wireless power transfer;
38.
A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology
机译:
PLL的系统验证行为模型,用于硅前验证和自上而下的设计方法
作者:
Lotfy Amr
;
Farooq Syed Feruz Syed
;
Wang Qi S.
;
Yaldiz Soner
;
Mosalikanti Praveen
;
Kurd Nasser
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
charge pump circuits;
phase detectors;
phase locked loops;
piecewise constant techniques;
table lookup;
AFS;
PLL model simulation;
PWC;
SSC;
adaptive frequency system;
charge-pump PLL;
phase detection;
phase noise;
piece-wise constant;
presilicon digital validation;
spread-spectrum clocking;
system-verilog behavioral model;
table lookup;
top-down design methodology;
transistor-level Spice simulations;
Adaptation models;
Clocks;
Correlation;
Integrated circuit modeling;
Phase locked loops;
Phase noise;
Voltage-controlled oscillators;
39.
A compact, high linearity 40GS/s track-and-hold amplifier in 90nm SiGe technology
机译:
采用90nm SiGe技术的紧凑型,高线性度40GS / s采样保持放大器
作者:
Lal Deeksha
;
Abbasi Morteza
;
Ricketts David S.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
Ge-Si alloys;
amplifiers;
analogue-digital conversion;
heterojunction bipolar transistors;
sample and hold circuits;
transceivers;
SiGe;
analog to digital converters;
heterojunction bipolar transistor technology;
high speed transceivers;
low distortion transceivers;
peak cutoff frequency biasing;
power 560 mW;
size 90 nm;
total harmonic distortion;
track-and-hold amplifier;
Clocks;
Frequency measurement;
Heterojunction bipolar transistors;
III-V semiconductor materials;
Indium phosphide;
Linearity;
Silicon germanium;
Analog to Digital Converter;
Linearity;
Optical Transcievers;
SiGe HBT;
Switched Emitter Follower;
Track and Hold;
mm wave radios;
40.
Ultra-low power multi-channel data conversion with a single SAR ADC for mobile sensing applications
机译:
具有单个SAR ADC的超低功耗多通道数据转换,适用于移动传感应用
作者:
Wenjuan Guo
;
Youngchun Kim
;
Tewfik Ahmed
;
Nan Sun
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
compressed sensing;
convex programming;
low-power electronics;
mobility management (mobile radio);
signal reconstruction;
wireless sensor networks;
CMOS process;
FoM;
Nyquist rate;
SAR ADC;
SNDR;
analog-to-digital converter;
bandwidth 500 kHz;
compressive sensing theory;
convex optimization method;
multichannel sparse signal conversion;
signal reconstruction;
size 0.13 mum;
ultra low power multichannel data conversion system;
Bandwidth;
Capacitors;
Greedy algorithms;
Hardware;
Mathematical model;
Mobile communication;
Sensors;
ADC;
SAR;
compressive sensing;
low power;
mobile sensing;
multi-channel;
41.
A low TC, supply independent and process compensated current reference
机译:
低TC,独立于电源和过程补偿的电流基准
作者:
Chundong Wu
;
Wang Ling Goh
;
Chiang Liang Kok
;
Wanlan Yang
;
Siek Liter
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
reference circuits;
CMOS process;
current 30 nA;
process compensation feature;
size 0.18 mum;
temperature -40 C to 80 C;
trim-free low temperature coefficient supply independent current reference;
voltage 2.4 V to 3.0 V;
Decision support systems;
CTAT;
Current reference;
PTAT;
process compensation;
supply independent;
temperature coefficient;
trim-free;
42.
A 10 mW 60GHz 65nm CMOS DCO with 24 tuning range and 40 kHz frequency granularity
机译:
具有24%调谐范围和40 kHz频率粒度的10 mW 60GHz 65nm CMOS DCO
作者:
Hussein Ahmed I.
;
Saberi Shadi
;
Paramesh Jeyanandh
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
inductors;
millimetre wave oscillators;
switched capacitor networks;
CMOS DCO;
capacitive degeneration;
coarse tuning;
current 10 mA;
fine frequency tuning resolution;
frequency 1 MHz;
frequency 10 MHz;
frequency 40 kHz;
frequency 48.1 GHz to 61.3 GHz;
mm-wave digitally controlled oscillator;
output shunt-peaking buffer;
power 10 mW;
size 65 nm;
switched coupled-inductor;
switched-capacitor banks;
very fine frequency tuning granularity;
voltage 1 V;
Decision support systems;
Hafnium;
Inductors;
ADPLL;
DCO;
Wide tuning range;
millimeter wave Frequency resolution;
switched coupled inductor;
43.
A single-inductor 7+7 ratio reconfigurable resonant switched-capacitor DC-DC converter with 0.1-to-1.5V output voltage range
机译:
具有0.1至1.5V输出电压范围的单电感器7 + 7比可重配置谐振开关电容器DC-DC转换器
作者:
Salem Loai G.
;
Mercier Patrick P.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
DC-DC power convertors;
current density;
inductors;
resonant power convertors;
switched capacitor networks;
3-level buck converters;
CMOS integrated circuit;
DC-DC converter;
arbitrary binary ratio;
current density;
flying capacitors;
frequency-scaled gear train SC topology;
gear ratio modulation;
inter-stage decoupling;
resonance Q-factor;
resonant converter;
single-inductor reconfigurable resonant switched-capacitor;
soft charging;
voltage 0.1 V to 1.5 V;
Capacitors;
Frequency modulation;
Gears;
Inductors;
Resonant frequency;
Switches;
DC-DC converter;
Power electronics;
resonant;
soft-charging;
switched-capacitor;
zero current switching;
44.
A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction
机译:
具有基于统计估计的降噪功能的10.5-b ENOB 645 nW 100kS / s SAR ADC
作者:
Long Chen
;
Xiyuan Tang
;
Sanyal Arindam
;
Yeonam Yoon
;
Jie Cong
;
Nan Sun
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
comparators (circuits);
digital-analogue conversion;
estimation theory;
integrated circuit design;
low-power electronics;
statistical analysis;
CMOS technology;
DAC;
LSB;
SAR ADC;
comparator noise reduction;
conversion residue estimation;
hardware complexity;
low-power comparator;
noise figure 7 dB;
power 645 nW;
power-efficient SNR enhancement technique;
quantization error;
size 65 nm;
statistical estimation;
voltage 0.7 V;
word length 10.5 bit;
Capacitors;
Clocks;
Estimation;
Noise reduction;
Quantization (signal);
Signal to noise ratio;
Standards;
45.
A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space
机译:
83fps 1080P分辨率354mW硅实现,用于计算仿射空间中改进的鲁棒功能
作者:
Shouyi Yin
;
Peng Ouyang
;
Leibo Liu
;
Shaojun Wei
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
affine transforms;
feature extraction;
image processing equipment;
integrated circuit design;
parallel processing;
TSMC process;
affine space;
feature vector computing;
full parallel Gaussian pyramid computing;
optimization technique;
power 354 mW;
reverse based pipelined affine computing;
robust feature;
rotation invariant binary pattern;
silicon implementation;
Computer architecture;
Filtering;
Hardware;
Histograms;
Robustness;
Silicon;
Throughput;
46.
A 14.4nW 122KHz dual-phase current-mode relaxation oscillator for near-zero-power sensors
机译:
一个用于接近零功率传感器的14.4nW 122KHz双相电流模式弛豫振荡器
作者:
Shanshan Dai
;
Rosenstein Jacob K.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
current-mode circuits;
low-power electronics;
relaxation oscillators;
CMOS technology;
digital clock;
frequency 122 kHz;
near-zero-power sensors;
power 14.4 nW;
size 0.18 mum;
temperature -20 C to 100 C;
ultra-low-power dual-phase current-mode relaxation oscillator;
voltage 0.6 V to 1.8 V;
CMOS integrated circuits;
Clocks;
Delays;
Oscillators;
Temperature measurement;
Temperature sensors;
current mode;
dual-phase;
low power;
low voltage;
relaxation oscillator;
temperature compensation;
47.
A 14.8μV
RMS
integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference
机译:
具有开关RC带隙基准的14.8μV
RMS inf>集成噪声输出无电容低压降稳压器
作者:
Magod Raveesh
;
Suda Naveen
;
Ivanov Vadim
;
Balasingam Ravi
;
Bakkaloglu Bertan
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
amplifiers;
controllers;
current-mode circuits;
energy gap;
sample and hold circuits;
switched capacitor filters;
current 40 muA;
current-mode chopped error amplifier techniques;
integrated noise output capacitor-less low dropout regulator;
linear supply regulators;
multi-loop error amplifier;
size 0.25 mum;
switched capacitor notch filter;
switched-RC sample-and-hold filtered bandgap reference;
unconditionally stable error amplifier;
voltage 1 V to 3.3 V;
voltage 230 mV;
Decision support systems;
Hafnium;
LDO;
capacitor-less;
chopping;
low dropout regulator;
low noise;
notch filter;
sample-and-hold;
48.
A 15 GHz-bandwidth 20dBm P
SAT
power amplifier with 22 PAE in 65nm CMOS
机译:
一个15 GHz带宽20dBm P
SAT inf>功率放大器,在65nm CMOS中具有22%的PAE
作者:
Junlei Zhao
;
Bassi Matteo
;
Mazzanti Andrea
;
Svelto Francesco
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
IEEE standards;
microwave amplifiers;
microwave integrated circuits;
power amplifiers;
power combiners;
CMOS;
IEEE820.15;
PAE;
PSAT power amplifier;
Wigig;
bandwidth 15 GHz;
coupled resonators;
frequency 58.5 GHz to 73.5 GHz;
gain 30 dB;
gain-bandwidth product;
power combiners;
power splitters;
size 65 nm;
Bandwidth;
Capacitors;
Gain;
Inductors;
Power combiners;
Power generation;
Resonant frequency;
49.
3.5–0.5V input, 1.0V output multi-mode power transformer for a supercapacitor power source with a peak efficiency of 70.4
机译:
3.5-0.5V输入,1.0V输出多模式电源变压器,用于超级电容器电源,峰值效率为70.4%
作者:
Xingyi Hua
;
Harjani Ramesh
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
DC-DC power convertors;
power transformers;
radiofrequency identification;
supercapacitors;
switched capacitor networks;
RFID;
TSMC GP process;
capacitance 80 mF;
current 3.3 muA;
efficiency 70.4 percent;
frequency 2.0 MHz;
multimode power transformer;
size 65 nm;
step-down converter;
step-up converter;
supercapacitor power source;
switched-capacitor DC-DC converter;
voltage 3.5 V to 0.5 V;
Clocks;
Power conversion;
Power transformers;
Switches;
Transistors;
Voltage measurement;
50.
A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration
机译:
具有基于VCO的积分器和数字DAC校准功能的0.04mm 2 sup> 0.9mW 71dB SNDR分布式模块化AS ADC
作者:
Yeonam Yoon
;
Kyoungtae Lee
;
Sungjin Hong
;
Xiyuan Tang
;
Long Chen
;
Nan Sun
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
calibration;
delta-sigma modulation;
integrating circuits;
voltage-controlled oscillators;
CMOS;
VCO-based closed-loop ΔΣ ADC;
bandwidth 1.7 MHz;
digital DAC mismatch calibration technique;
distributed modular architecture;
dual VCO-based integrator;
intrinsic CLA capability;
intrinsic clocked averaging capability;
power 0.9 mW;
repetitive slices;
size 130 nm;
voltage 1.2 V;
CMOS integrated circuits;
Calibration;
Computer architecture;
Delays;
Gain;
Layout;
Voltage-controlled oscillators;
51.
A 16-channel, 1-second latency patient-specific seizure onset and termination detection processor with dual detector architecture and digital hysteresis
机译:
具有双检测器架构和数字磁滞的16通道,1秒延迟的患者特定的发作和终止检测处理器
作者:
Chen Zhang
;
Awais Bin Altaf Muhammad
;
Yoo Jerald
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
electroencephalography;
frequency division multiplexing;
learning (artificial intelligence);
patient monitoring;
support vector machines;
digital hysteresis;
dual detector architecture;
frequency-time division multiplexing filter architecture;
latency patient-specific seizure onset;
linear support vector machine classifiers;
patient-specific machine learning techniques;
termination detection processor;
Decision support systems;
digital hysteresis;
dual detector architecture;
epileptic seizure;
machine learning;
scalp electroencephalography (EEG);
seizure onset and termination detection;
52.
A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM
机译:
具有固有DEM的65nm CMOS中的0.073mm 2 sup> 10-GS / s 6位时域折叠ADC
作者:
Shuang Zhu
;
Benwei Xu
;
Bo Wu
;
Soppimath Kiran
;
Yun Chiu
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS digital integrated circuits;
oscillators;
time-digital conversion;
time-domain analysis;
CMOS process;
Nyquist input;
RO;
TDC;
area-efficient time-domain conversion technique;
back-end complexity;
built-in dynamic element matching feature;
clock-skew calibration;
front-end single-VTC;
front-end single-voltage-to-time converter;
inherent DEM;
inherent folding effect;
ring oscillator;
silicon area;
size 65 nm;
time-domain folding ADC;
time-interleaved ADC;
time-to-digital converter;
word length 6 bit;
Clocks;
Delays;
Discharges (electric);
Partial discharges;
Quantization (signal);
Time-domain analysis;
folding ADC;
time amplifier;
time domain;
time-to-digital converter;
voltage-to-time converter;
53.
A seizure-detection IC employing machine learning to overcome data-conversion and analog-processing non-idealities
机译:
癫痫发作检测IC,采用机器学习技术来克服数据转换和模拟处理的非理想性
作者:
Jintao Zhang
;
Liechao Huang
;
Zhuo Wang
;
Verma Naveen
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
electroencephalography;
feature extraction;
learning (artificial intelligence);
medical signal processing;
readout electronics;
CMOS integrated circuit;
EEG feature extraction;
analog multiplication;
analog processing nonidealities;
data conversion nonidealities;
electroencephalogram signal readout;
machine learning algorithm;
seizure detection integrated circuit;
size 32 nm;
Decision support systems;
Machine learning;
analog processing circuits;
electroencephalography;
epilepsy;
error compensation;
system-on-chip;
54.
A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies
机译:
具有用户定义尺寸的技术不可知MTJ SPICE模型,用于STT-MRAM可扩展性研究
作者:
Jongyeon Kim
;
An Chen
;
Behin-Aein Behtash
;
Kumar Saurabh
;
Jian-Ping Wang
;
Kim Chris H.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
MRAM devices;
SPICE;
magnetic tunnelling;
STT-MRAM;
in-plane MTJ;
perpendicular MTJ;
realistic MTJ characteristics;
self-contained MTJ SPICE model;
self-contained magnetic tunnel junction SPICE model;
spin-transfer torque MRAM;
user-defined input parameters;
user-friendly SPICE model;
Anisotropic magnetoresistance;
Integrated circuit modeling;
Magnetic tunneling;
Mathematical model;
SPICE;
Switches;
Tunneling magnetoresistance;
55.
A 16nm configurable pass-gate bit-cell register file for quantifying the V
MIN
advantage of PFET versus NFET pass-gate bit cells
机译:
一个16nm可配置的传输门位单元寄存器文件,用于量化PFET与NFET传输门位单元的V
MIN inf>优势
作者:
Jihoon Jeong
;
Atallah Francois
;
Nguyen Hoan
;
Puckett Josh
;
Bowman Keith
;
Hansquine David
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
MOSFET;
CMOS circuit-design;
FinFET technology;
NFET drive current;
NFET pass-gate bit cells;
PFET drive current;
PFET pass-gate bit cells;
configurable pass-gate bit-cell register file;
silicon test-chip measurement;
size 16 nm;
transmission-gate;
Decision support systems;
56.
A voltage doubling passive rectifier/regulator circuit for biomedical implants
机译:
用于生物医学植入物的倍压无源整流器/调节器电路
作者:
Lee Edward K. F.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
amplifiers;
prosthetic power supplies;
rectifying circuits;
voltage multipliers;
voltage regulators;
CMOS process;
auxiliary rectifier;
biomedical implants;
bulk voltage;
efficiency 87.7 percent;
error amplifier;
gate voltage;
linear regulator;
output transistor;
power 46.8 mW;
time 0.18 mus;
voltage 6 V;
voltage doubling passive rectifier-regulator circuit;
voltage doubling prectulator;
Implants;
Rectifiers;
Regulators;
Schottky diodes;
Transistors;
Voltage control;
Voltage measurement;
57.
A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology
机译:
采用65nm CMOS技术的190mW 40Gbps SerDes发送器和接收器芯片组
作者:
Ke Huang
;
Deng Luo
;
Ziqiang Wang
;
Xuqiang Zheng
;
Fule Li
;
Chun Zhang
;
Zhihua Wang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
MMIC;
comparators (circuits);
phase detectors;
transceivers;
BER;
CDR;
CMOS;
SerDes;
bang-bang phase detector;
bit rate 40 Gbit/s;
cascaded dynamic comparators;
current-integrating FFE;
frequency 1 MHz;
loss 15 dB;
phase noise;
power 190 mW;
power-efficient front-end circuits;
receiver chipset;
size 65 nm;
time 26 ps;
time 6.7 ps;
transceiver;
transmitter chipset;
Bit error rate;
Clocks;
Jitter;
Latches;
Receivers;
Timing;
Transmitters;
CDR;
FFE;
SerDes;
low power;
58.
A 0.1–5.0GHz self-calibrated SDR transmitter with −62.6dBc CIM3 in 65nm CMOS
机译:
在65nm CMOS中具有-62.6dBc CIM3的0.1–5.0GHz自校准SDR发送器
作者:
Yun Yin
;
Yanqiang Gao
;
Zhihua Wang
;
Baoyong Chi
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
Long Term Evolution;
microwave receivers;
mixers (circuits);
power control;
radio transmitters;
software radio;
3rd-order nonlinearity cancellation;
CMOS integrated circuit;
GSM-EDGE-LTE signals;
LO leakage;
LTE band42;
RF operation frequency deviation;
RF operation frequency self-tuning;
V-I converter;
class-AB/F dual-mode PA;
complete self-calibration scheme;
frequency 0.1 GHz to 5.0 GHz;
image rejection;
nonideal effects;
output power control;
power mixer front-end;
self-calibrated SDR transmitter;
size 65 nm;
software-defined radios;
Calibration;
Mixers;
Narrowband;
Power generation;
Radio frequency;
Transistors;
Transmitters;
59.
A 1A, 20MHz/100MHz dual-inductor 4-output buck converter with fully-integrated bond-wire-based output filters for ripple reduction
机译:
一个1A,20MHz / 100MHz双电感4输出降压转换器,具有完全集成的基于键合线的输出滤波器,可降低纹波
作者:
Yongjie Jiang
;
Fayed Ayman
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
DC-DC power convertors;
VHF filters;
lead bonding;
radiofrequency integrated circuits;
2-phase input stage;
CMOS technology;
DC-DC power converters;
DF-DIMO buck converter;
current 1 A;
current 125 mA;
current 250 mA;
dual-frequency dual-inductor multiple-output buck converter;
dual-inductor 4-output buck converter;
dynamic voltage scaling;
frequency 100 MHz;
frequency 20 MHz;
fully-integrated bond-wire-based output filters;
size 65 nm;
time 60 ns;
voltage 0.5 V;
voltage ripple reduction;
Capacitors;
Digital signal processing;
Inductors;
Switches;
System-on-chip;
Topology;
Voltage control;
DC-DC power converters;
SIMO power converters;
dynamic voltage scaling;
switching regulators;
60.
A 0.4V∼1V 0.2A/mm2 70 efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS
机译:
具有0.4V〜1V 0.2A / mm 2 sup> 70%效率的500MHz完全集成的数字控制3级降压稳压器,具有在22nm三栅极CMOS上的片上高密度MIM电容器
作者:
Kumar Pavan
;
Vaidya Vaibhav A.
;
Krishnamurthy Harish
;
Kim Stephen
;
Matthew George E.
;
Weng Sheldon
;
Thiruvengadam Bharani
;
Proefrock Wayne
;
Ravichandran Krishnan
;
De Vivek
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
MIM devices;
UHF integrated circuits;
capacitors;
inductors;
power convertors;
voltage regulators;
3-level converter;
DVFS;
VR;
dynamic voltage frequency scaling;
efficiency 70 percent to 72 percent;
frequency 500 MHz;
fully integrated digitally controlled 3-level buck voltage regulator;
monolithic integration;
on-die high density MIM capacitor;
on-die spiral inductor;
power density;
scalability;
size 22 nm;
trigate CMOS technology;
voltage 0.4 V to 1 V;
3-Level Buck;
Power Integrated Circuits;
buck VR;
circuit topology;
digital control;
voltage regulators;
61.
A 0.6-V, 30-GHz six-phase VCO with superharmonic coupling in 32-nm SOI CMOS technology
机译:
具有32nm SOI CMOS技术的超谐波耦合功能的0.6V,30GHz六相VCO
作者:
Dongseok Shin
;
Raman Sanjay
;
Kwang-Jin Koh
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
silicon-on-insulator;
voltage-controlled oscillators;
SOI CMOS technology;
frequency 29.24 GHz to 31.56 GHz;
frequency 31.43 GHz;
inductive network;
power 1.52 mW;
six-phase VCO;
size 32 nm;
superharmonic coupling;
tail noise filter;
Couplings;
Frequency measurement;
Harmonic analysis;
Inductors;
Phase noise;
Power harmonic filters;
Voltage-controlled oscillators;
32-nm SOI;
CMOS;
VCO;
coupled inductors;
multiphase;
oscillator;
superharmonic coupling;
62.
A 110nA quiescent current buck converter with zero-power supply monitor and near-constant output ripple
机译:
具有零电源监控器和接近恒定输出纹波的110nA静态电流降压转换器
作者:
Danzhu Lu
;
Suyi Yao
;
Bin Shao
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
DC-DC power convertors;
comparators (circuits);
CMOS process;
adaptive-bias hysteresis comparator;
current 1 muA;
current 110 nA;
current 5 muA to 100 mA;
efficiency 78 percent;
near-constant output ripple;
quiescent current buck converter;
size 0.35 mum;
ultra-low power application;
zero IQ pull-down structure;
zero-power supply monitor;
Capacitors;
Hysteresis;
Low-power electronics;
Monitoring;
Threshold voltage;
Voltage control;
Wireless sensor networks;
Ultra-low power buck converter;
adaptive-bias comparator;
zero IQ pull-down structure;
63.
A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0–1 MASH ADC with direct digital background nonlinearity calibration
机译:
具有直接数字背景非线性校准的基于VCO的12b ENOB,2.5MHz-BW,4.8mW 0-1 MASH ADC
作者:
Ragab Kareem
;
Nan Sun
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
calibration;
digital-analogue conversion;
voltage-controlled oscillators;
CMOS;
SNDR;
VCO gain error;
VCO-based 0-1 MASH ΣΔ ADC;
bandwidth 2.5 MHz;
capacitor mismatch;
direct digital background calibration technique;
nonlinearity errors;
power 4.8 mW;
residue generating DAC;
size 180 nm;
time 64 ms;
voltage 1.8 V;
word length 12 bit;
Calibration;
Convergence;
Gain;
Multi-stage noise shaping;
Quantization (signal);
Transfer functions;
Voltage-controlled oscillators;
Analog-to-digital converters;
background calibration;
voltage controlled oscillator;
64.
A 0.622–10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOS
机译:
0.622–10Gb / s无电感器自适应线性均衡器,具有频谱跟踪功能,可在0.13μmCMOS中实现数据速率自适应
作者:
Ray Sagar
;
Hella Mona M.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
adaptive equalisers;
calibration;
circuit feedback;
CMOS technology;
adaptive equalizer;
bit rate 10 Gbit/s;
dual-loop balancing technique;
equalizer boost;
optimal equalization;
power 130 mW;
self-calibration;
servo loop;
size 0.13 mum;
spectral balancing circuit;
third order nested feedback equalizing filter;
voltage 1.2 V;
Adaptive equalizers;
Bit error rate;
CMOS integrated circuits;
CMOS technology;
Frequency control;
Voltage control;
65.
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
机译:
具有32nm SOI CMOS的1.8pJ / bit 16×16-Gb / s源同步并行接口,具有用于链路重新校准的接收器冗余
作者:
Dickson Timothy O.
;
Yong Liu
;
Agrawal Ankur
;
Bulzacchelli John F.
;
Ainspan Herschel
;
Toprak-Deniz Zeynep
;
Parker Benjamin D.
;
Meghelli Mounir
;
Friedman Daniel J.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
current mirrors;
inductors;
phase locked loops;
silicon-on-insulator;
8-phase clocking;
Megtron-6;
PLL;
SOI CMOS;
Si;
TX serializer;
active-inductor-based RX CTLE;
bit rate 256 Gbit/s;
bus-level receiver;
current mirrors;
current-integrating phase interpolator cores;
link recalibration;
phase locked loops;
phase rotator;
receiver redundancy;
size 32 nm;
source synchronous parallel interface;
source-synchronous I/O;
CMOS integrated circuits;
Calibration;
Clocks;
Computer architecture;
Receivers;
Rotation measurement;
Timing;
66.
A 130nm canary SRAM for SRAM dynamic write V
MIN
tracking across voltage, frequency, and temperature variations
机译:
130nm金丝雀SRAM,用于SRAM动态写入V
MIN inf>跟踪电压,频率和温度变化
作者:
Banerjee Arijit
;
Breiholz Jacob
;
Calhoun Benton H.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
SRAM chips;
semiconductor technology;
SRAM VMIN scaling;
bitline type;
bulk technology;
canary SRAM;
peripheral assist techniques;
size 130 nm;
wordline type;
Decision support systems;
US Department of Defense;
Yttrium;
Canary SRAM;
SRAM dynamic write VinfMIN/inf tracking;
wordline and bitline type reverse assist;
67.
A 14-bit 0.17mm2 SAR ADC in 0.13μm CMOS for high precision nerve recording
机译:
用于0.13μmCMOS的14位0.17mm 2 sup> SAR ADC,用于高精度神经记录
作者:
Anh Tuan Nguyen
;
Jian Xu
;
Zhi Yang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
biomedical electronics;
electromyography;
low-power electronics;
analog-digital converter;
area-efficient CMOS integrated circuit;
high precision nerve recording;
power 10 muW;
power-efficient ADC;
size 0.13 mum;
successive approximate register;
Arrays;
Calibration;
Capacitors;
Error analysis;
Estimation;
Power demand;
System-on-chip;
High-resolution SAR ADC;
capacitor mismatches estimation and calibration;
half-split DAC array;
high precision nerve recording;
68.
A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS
机译:
采用28 nm SOI CMOS的20 Gb / s 0.3 pJ / b单端芯片对芯片收发器
作者:
Dehlaghi Behzad
;
Carusone Anthony Chan
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS logic circuits;
elemental semiconductors;
equalisers;
integrated circuit packaging;
low-power electronics;
silicon;
silicon-on-insulator;
transceivers;
STM FD-SOI CMOS logic-style circuit technology;
Si;
bit rate 16.4 Gbit/s;
bit rate 20 Gbit/s;
clocking circuit;
loss 10.7 dB;
loss 12.9 dB;
loss 5.9 dB;
loss 7.1 dB;
low-power transceiver architecture;
packaging bump;
passive equalizer;
power consumption;
single-ended die-to-die transceiver;
single-ended signaling;
size 28 nm;
transmitter;
Bandwidth;
CMOS integrated circuits;
Clocks;
Multiplexing;
Receivers;
Transceivers;
Transmitters;
69.
A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT
机译:
在0.25um GaN HEMT中保持200-MS / s的98dB SNR保持
作者:
SungWon Chung
;
Hae-Seung Lee
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
III-V semiconductors;
Schottky diodes;
high electron mobility transistors;
sample and hold circuits;
wide band gap semiconductors;
GaN;
HEMT;
SNR;
Schottky diode;
T/H circuit;
asymmetric gate device;
current 195 mA;
high electron mobility transistor;
signal-noise ratio;
size 0.25 mum;
track-and-hold circuit;
voltage 20 V;
Decision support systems;
Hafnium;
GaN HEMT;
Schottky diode;
Track-and-hold;
70.
A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technology
机译:
采用65nm CMOS技术的201 mV / pH,375 fps和512×576 CMOS ISFET传感器
作者:
Yu Jiang
;
Xu Liu
;
Xiwei Huang
;
Jing Guo
;
Mei Yan
;
Hao Yu
;
Jui-Cheng Huang
;
Cheng-Hsiang Hsieh
;
Tung-Tsun Chen
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
DNA;
analogue-digital conversion;
biological techniques;
genomics;
ion sensitive field effect transistors;
pH measurement;
readout electronics;
CMOS sensor;
DNA sequencing;
ISFET sensor;
ion sensitive field effect transistor sensor;
pH-to-time-to-voltage conversion;
readout electronics;
single slope ADC;
Arrays;
CMOS integrated circuits;
Capacitance;
Decoding;
Passivation;
Sensitivity;
Sensors;
71.
A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm
机译:
使用65nm的基于ROM的S盒的275 Gbps AES加密加速器
作者:
Erbagci Burak
;
Akkaya Nail Etkin Can
;
Teegarden Craig
;
Mai Ken
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS logic circuits;
cryptography;
logic gates;
pipeline arithmetic;
read-only storage;
AES algorithm;
AES encryption accelerator;
CMOS;
CTR;
ROM based S-boxes;
SubBytes step;
advanced encryption standard;
bit rate 275 Gbit/s;
counter-mode operation;
frequency 2.2 GHz;
logic gate S-Box;
pipelined AES-128 encryption accelerator;
power 523 mW;
size 65 nm;
temperature 27 degC;
voltage 1.0 V;
Clocks;
Decoding;
Encryption;
Logic gates;
Read only memory;
Throughput;
72.
A 28-GHz inverse class-F power amplifier with coupled-inductor based harmonic impedance modulator
机译:
具有基于耦合电感的谐波阻抗调制器的28 GHz反向F类功率放大器
作者:
Mortazavi Seyed Yahya
;
Kwang-Jin Koh
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
BiCMOS analogue integrated circuits;
Ge-Si alloys;
MMIC power amplifiers;
coils;
coupled circuits;
inductors;
modulators;
2nd harmonic load impedance;
2nd harmonic reactive impedance;
3rd harmonic load impedance;
3rd harmonic reactive impedance;
BiCMOS technology;
PA;
SiGe;
coupled coil;
coupled-inductor;
efficiency 40 percent to 42 percent;
frequency 27.5 GHz to 29 GHz;
frequency-dependent inductance;
gain 64 dB;
harmonic impedance modulator;
inverse class-F-1 power amplifier;
power 50 mW;
size 0.13 mum;
Harmonic analysis;
Impedance;
Inductance;
Inductors;
Power amplifiers;
Resonant frequency;
Silicon germanium;
28 GHz;
38 GHz;
5 G LTE;
Class-AB;
SiGe;
class-F;
inverse class-F;
millimeter wave;
power amplifier;
73.
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor
机译:
采用298-fJ / writecycle / 650-fJ / readcycle 8T三端口SRAM的28-nm FD-SOI工艺技术,用于图像处理器
作者:
Mori Haruki
;
Nakagawa T.
;
Kitahara Y.
;
Kawamoto Y.
;
Takagi K.
;
Yoshimoto S.
;
Izumi S.
;
Nii K.
;
Kawaguchi H.
;
Yoshimoto M.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
SRAM chips;
elemental semiconductors;
image processing equipment;
logic circuits;
silicon;
silicon-on-insulator;
FD-SOI Process Technology;
Si;
eight-transistor bitcell;
frequency 18.2 MHz;
image memory processor;
logic circuit;
low voltage three-port SRAM;
one write-two-read port;
size 28 nm;
storage capacity 64 Kbit;
time 140 ns;
time 55 ns;
voltage 0.46 V;
voltage 0.54 V;
Logic circuits;
Logic gates;
SRAM cells;
Semiconductor device measurement;
Transistors;
Yttrium;
28-nm;
8T;
FD-SOI;
Image Memory;
Majority Logic;
Multiport SRAM;
74.
A 2–24GHz 360° full-span differential vector modulator phase rotator with transformer-based poly-phase quadrature network
机译:
具有基于变压器的多相正交网络的2–24GHz 360°全跨度差分矢量调制器相位旋转器
作者:
Tso-Wei Li
;
Jong Seok Park
;
Hua Wang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
differential amplifiers;
interpolation;
modulators;
accurate differential quadrature signals;
frequency 2 GHz to 24 GHz;
full span phase interpolation;
full-span differential vector modulator phase rotator;
linear digital variable gain amplifiers;
phase interpolation code;
size 65 nm;
transformer-based poly-phase quadrature network;
wideband poly-phase network;
Couplers;
Indexes;
Interpolation;
Radiofrequency integrated circuits;
Phase array;
phase shifter;
poly-phase network;
quadrature generation;
75.
A 5–115V efficiency-enhanced synchronous LED driver with adaptive resonant timing control
机译:
具有自适应谐振时序控制的5–115V效率增强型同步LED驱动器
作者:
Zhidong Liu
;
Hoi Lee
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
DC-DC power convertors;
adaptive control;
driver circuits;
light emitting diodes;
zero voltage switching;
DC-DC based synchronous LED driver;
adaptive resonant timing control;
efficiency 94.4 percent;
efficiency-enhanced synchronous LED driver;
high-frequency soft switching;
high-speed HV body-diode-based zero-voltage detectors;
optimal dead-time;
soft-switching mode;
switching loss;
voltage 5 V to 115 V;
zero-voltage switching;
Yttrium;
76.
A 72μW, 2.4GHz, 11.7 tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS
机译:
65nm CMOS中的72μW,2.4GHz,11.7%调谐范围,212dBc / Hz FoM LC-VCO
作者:
Joo-Myoung Kim
;
Jae-Seung Lee
;
Suna Kim
;
Taeik Kim
;
Hojin Park
;
Sang-Gug Lee
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS analogue integrated circuits;
LC circuits;
MIM devices;
UHF integrated circuits;
UHF oscillators;
inductors;
integrated circuit noise;
low-power electronics;
phase noise;
varactors;
voltage-controlled oscillators;
CMOS technology;
FoM LC-VCO;
LC-tank;
MIM capacitor array;
Q-factor degradation factor;
frequency 2.35 GHz to 2.64 GHz;
high-Q inductor;
high-Q oscillator;
phase noise;
positioning analysis;
power 72 muW;
size 65 nm;
varactor;
voltage 0.6 V;
Arrays;
MIM capacitors;
Q-factor;
Tuning;
Varactors;
Voltage-controlled oscillators;
BAW;
FBAR;
inductor;
phase noise;
quality factor;
varactor;
voltage-controlled oscillator;
77.
A 3.9 mW, 35–44/41–59.5 GHz distributed injection locked frequency divider
机译:
3.9 mW,35–44 / 41–59.5 GHz分布式注入锁定分频器
作者:
Imani Alireza
;
Hashemi Hossein
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
BiCMOS integrated circuits;
Ge-Si alloys;
bipolar MIMIC;
bipolar transistor circuits;
frequency dividers;
heterojunction bipolar transistors;
millimetre wave frequency convertors;
semiconductor materials;
BiCMOS HBT technology;
SiGe;
distributed injection locked frequency divider;
frequency 35 GHz to 59.5 GHz;
mm-wave frequency;
power 3.9 mW;
size 130 nm;
voltage 1.1 V;
Frequency conversion;
Frequency measurement;
Phase noise;
Power transmission lines;
Sensitivity;
Wideband;
Injection locked frequency Divider;
divide-by-two circuit;
locking range;
mm-wave;
78.
A 30.1μm2, < ±1.1°C-3σ-error, 0.4-to-1.0V temperature sensor based on direct threshold-voltage sensing for on-chip dense thermal monitoring
机译:
基于直接阈值电压检测的30.1μm 2 sup>,<±1.1°C-3σ误差,0.4至1.0V温度传感器,用于片上密集热监控
作者:
Seongjong Kim
;
Mingoo Seok
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
integrated circuit design;
integrated circuit packaging;
temperature sensors;
thermal management (packaging);
digital VLSI systems;
direct threshold voltage sensing;
on-chip dense thermal monitoring;
size 65 nm;
temperature sensor;
threshold voltage temperature dependency;
voltage 0.4 V to 1 V;
voltage-scalable design;
Monitoring;
Temperature dependence;
Temperature sensors;
Threshold voltage;
Very large scale integration;
79.
A 4.6mW, 22dBm IIP3 all MOSCAP based 34–314MHz tunable continuous time filter in 65nm
机译:
一个基于MOSCAP的4.6mW,22dBm IIP3、34nm至314MHz可调65nm连续时间滤波器
作者:
Palani Rakesh Kumar
;
Harjani Ramesh
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
MOS capacitors;
continuous time filters;
intermodulation distortion;
invertors;
software radio;
3rd order inverter;
MOS capacitor;
MOSCAP based tunable continuous time filter;
TSMC technology;
channel select filter;
current 4.2 mA;
filter capacitors;
frequency 34 MHz to 314 MHz;
intermodulation distortion;
inverter based filter;
load capacitance;
negative feedback network;
power 4.6 mW;
power supply;
size 65 nm;
software defined radios;
voltage 1.1 V;
Capacitors;
Computer architecture;
Impedance;
Inverters;
Negative feedback;
Resistors;
Transconductance;
80.
A Cartesian feedback-feedforward transmitter IC in 130nm CMOS
机译:
130nm CMOS的笛卡尔反馈前馈发射机IC
作者:
Sungmin Ock
;
Hyejeong Song
;
Gharpurey Ranjit
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS analogue integrated circuits;
UHF integrated circuits;
UHF power amplifiers;
feedback amplifiers;
feedforward amplifiers;
16 QAM LTE signal;
ACLR improvement;
CMOS technology;
Cartesian feedback-feedforward transmitter IC;
PA;
bandwidth 1.4 MHz;
error signal utilization;
frequency 2.4 GHz;
gain 8.7 dB;
open-loop transmitter;
power amplifier;
size 130 nm;
Bandwidth;
Distortion;
Feedback loop;
Feedforward neural networks;
Integrated circuits;
Linearity;
Prototypes;
Cartesian feedback;
Cartesian feedback-feedforward;
linearity;
power amplifier(PA);
transmitter(TX);
81.
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9ps
rms
integrated-jitter
机译:
具有1.9ps
rms inf>集成抖动的4mW宽带基于环的分数n DPLL
作者:
Elkholy Ahmed
;
Saxena Saurabh
;
Nandwana Romesh Kumar
;
Elshazly Amr
;
Hanumolu Pavan Kumar
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS digital integrated circuits;
MMIC oscillators;
delta-sigma modulation;
digital filters;
digital phase locked loops;
field effect MMIC;
interference suppression;
jitter;
phase noise;
voltage-controlled oscillators;
ΔΣ DAC quantization noise;
CMOS process;
dual-path digital loop filter architecture;
frequency 4 GHz to 5.5 GHz;
integrated-jitter;
measured in-band phase noise;
noise cancellation techniques;
power 4 mW;
ring VCO;
size 65 nm;
time 1.9 ps;
wide bandwidth ring oscillator-based fractional-n DPLL;
Bandwidth;
Frequency measurement;
Jitter;
Phase locked loops;
Phase noise;
Quantization (signal);
Ring oscillators;
DCO;
DPLL;
DTC;
Fractional-N;
TDC;
fractional divider;
jitter;
ring VCO;
time amplifier;
82.
A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS
机译:
在65nm CMOS中具有远端串扰消除和无分频器时钟生成功能的4×20 Gb / s 0.86pJ / b / lane 2-tap-FFE源串联终端发送器
作者:
Shuai Yuan
;
Liji Wu
;
Ziqiang Wang
;
Xuqiang Zheng
;
Wen Jia
;
Chun Zhang
;
Zhihua Wang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
clocks;
crosstalk;
equalisers;
feedforward;
interference suppression;
jitter;
transmitters;
2-inch channels;
2-tap-FFE source-series-terminated transmitter;
BER;
CMOS technology;
DDJ;
FEXT cancellation;
SST transmitter;
XTC;
crosstalk canceller;
dividerless clock generation;
far-end crosstalk cancellation;
feedforward equalizer;
peak-to-peak data dependent jitter;
size 65 nm;
Decision support systems;
CMOS;
FEXT cancellation;
FFE;
SST;
divider-less;
transmitter;
83.
A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface
机译:
用于频分复用存储器接口的5.4mW 4 Gb / s 5频段QPSK收发器
作者:
Wei-Han Cho
;
Yilei Li
;
Yanghyo Kim
;
Po-Tsang Huang
;
Yuan Du
;
Sheau Jiung Lee
;
Chang Mau-Chung Frank
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS memory circuits;
current-mode circuits;
frequency division multiplexing;
quadrature phase shift keying;
three-dimensional integrated circuits;
transceivers;
QPSK transceiver;
differential current-mode signaling;
frequency-division multiplexing memory interface;
on-chip TSV emulator;
orthogonal communication channels;
power 5.4 mW;
size 40 nm;
Bit error rate;
CMOS integrated circuits;
Frequency division multiplexing;
Phase shift keying;
Real-time systems;
Transceivers;
BER testing platform;
RF interconnects;
current-mode Schmitt trigger;
multi-band transceiver;
84.
A 51 pW reference-free capacitive-discharging oscillator architecture operating at 2.8 Hz
机译:
51 pW无基准电容放电振荡器架构,工作频率为2.8 Hz
作者:
Hui Wang
;
Mercier Patrick P.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS analogue integrated circuits;
MOSFET;
capacitors;
frequency stability;
low-power electronics;
radiofrequency integrated circuits;
radiofrequency oscillators;
CMOS process;
frequency 2.8 Hz;
gate-leakage transistor;
gate-leakage-based Hz-range oscillator;
power 51 pW;
power-expensive reference;
reference-free capacitive-discharging oscillator architecture;
size 65 nm;
temperature -40 degC to 60 degC;
temperature stable discharging path;
ultralow-power frequency-stable operation;
Accuracy;
Capacitors;
Circuit stability;
Logic gates;
Oscillators;
Thermal stability;
Transistors;
Ultra-low power;
gate-leakage;
oscillator;
temperature-stable;
timer;
85.
A 550μm2 CMOS temperature sensor using self-discharging P-N diode with ±0.1°C (3σ) calibrated and ±0.5°C (3σ) uncalibrated inaccuracies
机译:
550μm 2 sup> CMOS温度传感器,采用自放电P-N二极管,校准后为±0.1°C(3σ),未经校准为±0.5°C(3σ)
作者:
Chowdhury Golam R.
;
Hassibi Arjang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
system-on-chip;
temperature sensors;
CMOS temperature sensor;
distributed thermal monitoring systems;
high-performance system-on-chips;
power 4 muW;
self-discharging P-N diode;
size 0.18 mum;
temperature 35 degC to 100 degC;
temperature-dependent reverse-bias current;
voltage 1.8 V;
CMOS integrated circuits;
Calibration;
Heating;
Indexes;
Standards;
Temperature measurement;
Yttrium;
CMOS;
delta-sigma;
diode;
temperature sensor;
thermal management;
86.
A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS
机译:
采用28nm CMOS的5GS / s 10b 76mW时间交错SAR ADC
作者:
Jie Fang
;
Thirunakkarasu Shankar
;
Xuefeng Yu
;
Silva-Rivas Fabian
;
Kwang Young Kim
;
Chaoming Zhang
;
Singor Frank
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS digital integrated circuits;
analogue-digital conversion;
buffer circuits;
comparators (circuits);
integrated circuit design;
CMOS technology;
LSB conversion cycles;
SNDR;
SNR;
THD;
Timingskew mismatches;
comparator noise;
decision errors;
design techniques;
digital background calibration;
gain mismatches;
high-speed reference buffer;
merged capacitor switching algorithm;
offset mismatches;
power 76 mW;
programmable delay;
reduced radix-2;
sampling clock;
sampling network;
size 28 nm;
time-interleaved SAR ADC;
top-plate sampling;
word length 10 bit;
word length 11 bit;
CMOS integrated circuits;
Calibration;
Capacitors;
Clocks;
Estimation;
Switches;
Timing;
ADC;
SAR;
comparator;
time-interleaved;
timing skew;
87.
A compressed-sensing sensor-on-chip incorporating statistics collection to improve reconstruction performance
机译:
包含统计信息收集功能以改善重建性能的压缩传感片上传感器
作者:
Behravan Vahid
;
Shuo Li
;
Glover Neil E.
;
Chia-Hung Chen
;
Shoaib Mohammed
;
Temes Gabor C.
;
Chiang Patrick Y.
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
compressed sensing;
signal reconstruction;
signal sampling;
SER;
compressed-sensing sensor-on-chip;
compression factor;
improve reconstruction performance;
reconstructing signals;
reconstruction accuracy;
sampling time;
signal-to-error;
statistics collection;
Biomedical measurement;
Clocks;
Compressed sensing;
DSL;
Electrocardiography;
Receivers;
Sensors;
compressed sensing;
reconstruction error;
sensor-on-chip;
statistics collection;
88.
A configurable 5.9 μW analog front-end for biosignal acquisition
机译:
用于生物信号采集的可配置5.9μW模拟前端
作者:
Tan Yang
;
Junjie Lu
;
Jahan M. Shahriar
;
Griffin Kelly
;
Langford Jeremy
;
Holleman Jeremy
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
1/f noise;
CMOS integrated circuits;
amplifiers;
biomedical electronics;
electrocardiography;
electroencephalography;
electromyography;
integrated circuit noise;
medical signal detection;
1/f noise;
AFE;
AP signal;
CMOS process;
CRCI;
ECG;
EEG;
EMG;
IBL;
action potential signal;
biopotential signal recording;
biosignal acquisition;
chopper-stabilized current-reuse complementary input;
configurable analog front-end;
electrocardiogram;
electroencephalogram;
electromyography;
frequency 0.7 Hz to 7 kHz;
gain 45.2 dB to 71 dB;
noise-power efficiency;
power 5.4 muW;
power 5.9 muW;
resistance 4.3 Mohm to 102 Mohm;
size 0.13 mum;
telescopic-cascode amplifier;
tunable impedance-boosting loop;
voltage 1.2 V;
Hafnium;
Current-reuse complimentary input (CRCI);
analog front-end (AFE);
biosignal acquisition;
chopper stabilized;
configurable;
89.
A dual-tank LC VCO topology approaching towards the maximum thermodynamically-achievable oscillator FoM
机译:
双罐LC VCO拓扑接近最大热力学可实现的振荡器FoM
作者:
Nikpaik Amir
;
Nabavi Abdolreza
;
Shirazi Amir Hossein Masnadi
;
Shekhar Sudip
;
Mirabbasi Shahriar
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS analogue integrated circuits;
MMIC oscillators;
field effect MMIC;
phase noise;
voltage-controlled oscillators;
CMOS process;
class-B/C/D/F oscillators;
dual-tank LC VCO topology;
figure-of-merit;
frequency 4.17 GHz to 4.95 GHz;
maximum thermodynamically-achievable oscillator FoM;
phase noise performance;
size 0.13 nm;
Logic gates;
RLC circuits;
Thermal noise;
Topology;
Transistors;
Voltage-controlled oscillators;
impulse sensitivity function;
low phase noise;
90.
A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS
机译:
基于闪存的非均匀采样ADC,可在65nm CMOS中实现数字抗混叠滤波器
作者:
Tzu-Fan Wu
;
Cheng-Ru Ho
;
Chen Mike Shuo-Wei
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
antialiasing;
digital filters;
quadrature amplitude modulation;
16 QAM;
CMOS;
SNR;
analog antialiasing filter;
analog-digital converter;
complementary metal oxide semiconductor;
digital antialiasing filter;
flash-based non-uniform sampling ADC;
quadrature amplitude modulation;
size 65 nm;
time 10 ps;
time quantizer;
unwanted blocker signal;
voltage quantizer;
word length 4 bit;
ADC;
Asynchronous processing;
alias free;
non-uniform sampling;
91.
A full-duplex wireless integrated transceiver for implant-to-air data communications
机译:
全双工无线集成收发器,用于植入-空中数据通信
作者:
Mirbozorgi S. Abdollah
;
Bahrami Hadi
;
Sawan Mohamad
;
Rusch Leslie
;
Gosselin Benoit
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
amplitude shift keying;
biological tissues;
biomedical telemetry;
data communication;
electronic data interchange;
filtering theory;
low noise amplifiers;
phase shift keying;
prosthetics;
radio transceivers;
ultra wideband communication;
BPSK;
IR-UWB;
ISM band;
LNA;
OOK receiver;
bidirectional high-data rate neural interface;
biological tissues;
bit rate 100 Mbit/s;
bit rate 500 Mbit/s;
downlink telemetry;
frequency 2.4 GHz;
full-duplex wireless integrated transceiver;
implant-to-air data communication;
implantable antenna;
low noise amplifier;
neural recording applications;
neural stimulation applications;
power 10.8 mW;
power 5 mW;
power 5.4 mW;
receiver;
spectrum filtering;
transmitted pulse shaping;
transmitter;
Binary phase shift keying;
Downlink;
Receivers;
Transceivers;
Transmitters;
Uplink;
Wireless communication;
Full-duplex transceiver;
High-density brain machine interface;
High-speed;
IR-UWB;
RFIC design;
Wireless data transmission;
92.
A fully synthesized 0.4V 77dB SFDR reprogrammable SRMC filter using digital standard cells
机译:
使用数字标准单元的全合成0.4V 77dB SFDR可重编程SRMC滤波器
作者:
Jun Liu
;
Fahmy Ahmed
;
Taewook Kim
;
Maghari Nima
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
MOSFET;
active filters;
analogue integrated circuits;
operational amplifiers;
active blocks;
analog biquad filter;
bandwidth 1.7 MHz to 2.5 MHz;
digital gates;
digital standard cells;
fully reprogrammable multistage opamp array;
fully synthesized SFDR reprogrammable SRMC filter;
matched-RC duty-cycle generator;
power 0.8 mW;
size 0.13 mum;
switched-R-MOSFET-C filter;
verilog code;
voltage 0.4 V;
voltage 1 V;
CMOS integrated circuits;
CMOS technology;
Clocks;
Decision support systems;
Digital filters;
Resistance;
Standards;
Analog filters;
amplifiers;
common-mode feedback;
duty-cycle sampling;
synthesis;
93.
A high-performance, yet simple to design, digital-friendly type-I PLL
机译:
高性能但易于设计的数字友好型I型PLL
作者:
Sharkia Ahmad
;
Aniruddhan Sankaran
;
Shekhar Sudip
;
Mirabbasi Shahriar
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
digital phase locked loops;
phase detectors;
sample and hold circuits;
CMOS integrated circuit;
cycle slipping;
digital level shifter;
frequency 2.2 GHz to 2.8 GHz;
lock range improvement;
lock time improvement;
phase frequency detector;
phase locked loops;
pulse width modulation;
sample and hold envelope detector;
type-1 PLL;
voltage booster;
Decision support systems;
Frequency measurement;
Phase frequency detector;
PFD;
Type-I PLL;
cycle-slipping;
low phase noise;
low-area;
low-power;
voltage booster;
94.
A highly linear dual-band mixed-mode polar power amplifier in CMOS with an ultra-compact output network
机译:
具有超紧凑输出网络的CMOS高线性双频混合模式极性功率放大器
作者:
Jong Seok Park
;
Song Hu
;
Yanjie Wang
;
Hua Wang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
UHF power amplifiers;
impedance matching;
microwave power amplifiers;
AM-AM distortions suppression;
AM-PM distortions suppression;
analog techniques;
bulk CMOS process;
digital techniques;
double even-harmonic rejection;
dual-band optimum load-pull impedance matching;
frequency 2.35 GHz;
frequency 2.6 GHz;
frequency 4.5 GHz;
frequency 4.7 GHz;
highly linear dual-band mixed-mode polar power amplifier;
parallel power combining;
size 65 nm;
ultra-compact single-transformer passive network;
Distortion;
Distortion measurement;
Dual band;
Frequency measurement;
Impedance matching;
Power generation;
Power measurement;
Digital;
dual-band;
mixed-mode;
power amplifiers;
transformer;
95.
A novel low cost, high performance and reliable silicon interposer
机译:
一种新颖的低成本,高性能和可靠的硅中介层
作者:
Yazdani Farhang
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
elemental semiconductors;
flip-chip devices;
integrated circuit design;
integrated circuit reliability;
microassembling;
printed circuit design;
reflow soldering;
silicon;
solders;
three-dimensional integrated circuits;
wafer level packaging;
2.5D-3D devices;
CSAM images;
FR-4 PCB;
Si;
cost analysis;
design flow;
eutectic solder balls;
flip chip;
high density devices;
high performance silicon interposer;
interposer test vehicle;
low cost silicon interposer;
multilayer organic build-up substrate;
reflow process;
reliable silicon interposer;
second level assembly;
size 310 mum;
solder joint reliability;
temperature cycle stress test;
thick rigid silicon substrate;
underfill effect;
wafer-level fan-out;
Assembly;
Copper;
Packaging;
Reliability;
Silicon;
Substrates;
2.5D/3D;
Assembly;
Cost;
Design;
Flip Chip;
Integration;
Package;
Reliability;
Silicon Interposer;
Substrate;
TSV;
Thermal Stress;
Underfill;
Warpage;
Yield;
96.
A novel switched-capacitor-filter based low-area and fast-locking PLL
机译:
一种新型的基于开关电容滤波器的低面积和快速锁定PLL
作者:
Amourah Mezyad
;
Whately Morgan
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
UHF filters;
UHF integrated circuits;
passive filters;
phase locked loops;
switched capacitor filters;
CMOS process;
LPF;
PLL;
SC filter;
capacitor multiplication effect;
fractional charge integration;
frequency 200 MHz to 2.0 GHz;
passive filter;
phase locked loop;
ring oscillator;
size 65 nm;
switched-capacitor-filter;
time 0.9 ps;
Indexes;
Phase locked loops;
Phase noise;
Silicon;
Voltage-controlled oscillators;
PLL;
fast lock PLL;
low area PLL;
switched capacitor filter;
97.
A circuit designer's guide to 5G mm-wave
机译:
电路设计师的5G毫米波指南
作者:
Niknejad Ali M.
;
Thyagarajan Siva
;
Alon Elad
;
Wang Yanjie
;
Hull Christopher
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
5G mobile communication;
MIMIC;
integrated circuit design;
radio transceivers;
5G millimeter wave communication;
circuit designer guide;
fifth generation standard;
fourth generation mobile phone standards;
transceiver design;
5G mobile communication;
Aperture antennas;
Bandwidth;
Interference;
Wireless communication;
5G;
mm-wave mobile;
mm-waves;
98.
A dual-band 802.11abgn/ac transceiver with integrated PA and T/R switch in a digital noise controlled SoC
机译:
在数字噪声控制SoC中集成了PA和T / R开关的双频802.11abgn / ac收发器
作者:
Yuan-Hung Chung
;
Che-Hung Liao
;
Chun-Wei Lin
;
Yi-Shing Shih
;
Chin-Fu Li
;
Meng-Hsiung Hung
;
Ming-Chung Liu
;
Pi-An Wu
;
Jui-Lin Hsu
;
Ming-Yeh Hsu
;
Sheng-Hao Chen
;
Po-Yu Chang
;
Chih-Hao Chen
;
Yu-Hsien Chang
;
Jun-Yu Chen
;
Tao-Yao Chang
;
Chien George
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
CMOS integrated circuits;
baluns;
low noise amplifiers;
microwave power amplifiers;
switches;
system-on-chip;
transceivers;
wideband amplifiers;
wireless LAN;
1P6M CMOS technology;
IQ mismatch;
LNA;
PA load-line;
T/R switch;
VHT80 MCS9;
WLAN;
adaptive biasing scheme;
balun;
bandwidth 80 MHz;
calibration;
complementary metal oxide semiconductor;
digital noise controlled SoC;
dual-band 802.11 abgn/ac transceiver;
filler cap;
frequency 2.4 GHz;
frequency 5 GHz;
frequency dependence;
integrated PA;
low noise amplifier;
modulation and coding scheme 9;
power amplifier;
power efficiency;
power island switch;
size 55 nm;
switching noise;
system-on-chip;
wireless local area network;
Bandwidth;
Baseband;
Impedance matching;
Modulation;
Receivers;
Switches;
Transceivers;
VHT80 (Very-High throughput 80MHz Bandwidth);
WLAN;
load-line;
99.
Advanced wireless power and data transmission techniques for implantable medical devices
机译:
适用于植入式医疗设备的高级无线电力和数据传输技术
作者:
Hyung-Min Lee
;
Kiani Mehdi
;
Ghovanloo Maysam
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
biomedical telemetry;
inductive power transmission;
prosthetics;
radiofrequency interference;
advanced wireless power transmission;
circuit techniques;
data transmission;
external power sources;
implantable medical devices;
link structures;
power carrier interference;
power delivery path;
power levels;
short-range wireless power transmission;
transceiver circuits;
wideband bidirectional data communication;
wireless data telemetry;
wireless power transfer;
wirelessly-powered IMD;
Data communication;
Decision support systems;
Rectifiers;
Robustness;
Skin;
Wireless communication;
100.
Design considerations of HBM stacked DRAM and the memory architecture extension
机译:
HBM堆叠DRAM的设计注意事项和存储器架构扩展
作者:
Dong Uk Lee
;
Kang Seol Lee
;
Yongwoo Lee
;
Kyung Whan Kim
;
Jong Ho Kang
;
Jaejin Lee
;
Jun Hyun Chun
会议名称:
《IEEE Custom Integrated Circuits Conference》
|
2015年
关键词:
DRAM chips;
integrated circuit design;
low-power electronics;
three-dimensional integrated circuits;
3D stacked memory structure;
8-Hi stacking;
HBM stacked DRAM design;
TSV process;
high bandwidth memory;
low power consumption;
memory architecture extension;
pseudochannel;
small form factor;
vertical stacking;
Assembly;
Bandwidth;
Memory architecture;
Random access memory;
Registers;
Resistance;
Stacking;
High-Bandwidth;
Microbump;
Multi-Channel;
Stacked Memory;
TSV;
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