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首页> 外文期刊>WSEAS Transactions on Information Science and Applications >On the Design of Time-Predictable Low-Leakage Cache Memory for Real-Time Embedded Systems
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On the Design of Time-Predictable Low-Leakage Cache Memory for Real-Time Embedded Systems

机译：实时嵌入式系统中时间可预测的低泄漏高速缓存的设计

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This paper presents a multidisciplinary study that aims at designing a time-predictable low-leakage cache memory for real-time embedded systems. Both state-preserving and state-destroying leakage-saving mechanisms have been tested on a superscalar processor with two-level cache hierarchy. Full system simulation has been used to examine leakage-saving capability of each mechanism. In addition, a statistical approach has been proposed to study processor's time-predictability under potential leakage-saving techniques. Furthermore, the performance of real-time embedded systems in presence of leakage-saving techniques has been thoroughly analyzed using Matlab/Simulink-based models. Each possible design alternative has been evaluated in terms of four parameters that include: average power saving, degree of predictability (DoP), loss of schedulability (LoS) and performance of the underlying embedded system. Our results have shown that applying a state-preserving leakage-saving mechanism on either first-level data cache or last-level unified cache provides the most viable design option. The first alternative has achieved an average power saving of 32.61%, a DoP of 93.05% and a LoS of 0% while the second alternative has achieved an average power saving of 50.21%, a DoP of 80.30% and a LoS of 13.68%. Moreover, neither of them has caused any disruption in the performance of the experimental embedded system models. Consequently, using a first-level data cache with a state-preserving leakage-saving mechanism represents the best feasible option for systems with very critical timing requirements while employing a state-preserving low-leakage last-level cache can be the suitable option for systems with soft timing requirements and stringent power constrains.
机译：本文提出了一项多学科研究，旨在为实时嵌入式系统设计时间可预测的低泄漏高速缓存。状态保留和破坏状态的泄漏节省机制均已在具有两级高速缓存层次结构的超标量处理器上进行了测试。完整的系统仿真已用于检查每种机构的节电能力。另外，已经提出了一种统计方法来研究在潜在的节省泄漏技术下处理器的时间可预测性。此外，已经使用基于Matlab / Simulink的模型彻底分析了具有防漏技术的实时嵌入式系统的性能。每个可能的设计替代方案已根据四个参数进行了评估，这些参数包括：平均节能，可预测性（DoP），可调度性损失（LoS）和底层嵌入式系统的性能。我们的结果表明，在第一级数据高速缓存或最后一级统一高速缓存上应用保留状态的泄漏节省机制可提供最可行的设计选项。第一种选择实现了平均节电32.61％，DoP为93.05％和LoS为0％，第二种选择实现了平均节电50.21％，DoP为80.30％和LoS为13.68％。而且，它们都没有对实验嵌入式系统模型的性能造成任何破坏。因此，对于具有非常严格的时序要求的系统，使用具有状态保留泄漏保护机制的第一级数据高速缓存代表了最佳可行的选择，而对于系统而言，采用状态保留低泄漏的最后一级高速缓存可能是合适的选择。具有软时序要求和严格的功率限制。

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