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首页> 外文期刊>WSEAS Transactions on Signal Processing >Reconfigurable Architecture of Systolic Array Processors for Real Time Remote Sensing Image Enhancement/Reconstruction
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Reconfigurable Architecture of Systolic Array Processors for Real Time Remote Sensing Image Enhancement/Reconstruction

机译：用于实时遥感图像增强/重建的脉动阵列处理器的可重配置架构

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摘要

In this paper, we propose a reconfigurable architecture of systolic array (SA) processors for near real time implementation of high-resolution reconstruction of remote sensing (RS) imagery. The proposed design is based on a Field Programmable Gate Array and performs the image enhancement/reconstruction tasks in an efficient reconfigurable processing architecture mode that involves the systolic array processors aimed to meet the (near) real time imaging systems requirements in spite of conventional computations. In particular, the reconfigurable architecture of SA processors is employed with the objective to decrease the computational load of the large-scale RS image enhancement/reconstruction tasks required to implement the RS enhancement/reconstruction algorithms based on the descriptive regularization techniques with the corresponding iterative fixed-point Projection Onto Convex Sets unified via the proposed Hardware/Software Co-Design paradigm.
机译：在本文中，我们提出了一种可重构结构的脉动阵列（SA）处理器，用于高分辨率（RS）图像的高分辨率重建的近实时实现。提出的设计基于现场可编程门阵列，并以有效的可重构处理架构模式执行图像增强/重建任务，该模式涉及脉动阵列处理器，尽管常规计算也旨在满足（近）实时成像系统要求。特别地，采用SA处理器的可重构体系结构的目的是减少基于具有描述性固定化的描述性正则化技术来实现RS增强/重构算法的大规模RS图像增强/重构任务的计算负荷。通过拟议的硬件/软件协同设计范例将点投影到凸集上。

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