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首页> 外文期刊>Journal of active and passive electronic devices >LEakage Control TRAnsistor (LECTRA): A novel Approach for Leakage Reduction in Low Power VLSI Design
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LEakage Control TRAnsistor (LECTRA): A novel Approach for Leakage Reduction in Low Power VLSI Design

机译：漏电控制晶体管（LECTRA）：一种用于低功耗VLSI设计的减少漏电的新颖方法

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摘要

A new circuit approach is proposed in this paper to reduce the sub threshold and gate oxide leakage power consumption in low power VLSI circuit design. This approach is useful in reducing leakage currents in active as well as standby modes of operation. Here two extra transistors are added one of which is high threshold voltage transistor and the other one is low threshold voltage transistor. High threshold voltage transistor is used as a primary device to reduce the leakage currents and for maintaining the performance of CMOS circuit. A low threshold voltage transistor is configured as a sleep transistor with PDN. Experiments conducted on a proposed circuit design using 180nm, 130nm, 45nm and 22nm TSMC ? using Tanner EDA tool. Results obtained shows significant reduction in leakage power when compared to well-known design approaches.
机译：本文提出了一种新的电路方法，以降低低功耗VLSI电路设计中的子阈值和栅极氧化物泄漏功耗。该方法可用于减少活动和待机操作模式下的泄漏电流。此处添加了两个额外的晶体管，其中一个是高阈值电压晶体管，另一个是低阈值电压晶体管。高阈值电压晶体管被用作主要器件，以减少泄漏电流并保持CMOS电路的性能。低阈值电压晶体管被配置为具有PDN的睡眠晶体管。在使用180nm，130nm，45nm和22nm台积电的电路设计中进行的实验使用Tanner EDA工具。与众所周知的设计方法相比，获得的结果表明泄漏功率大大降低。

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