Achieving ultra-shallow junctions in future CMOS devices by a wet processing technique

Barnett J.; Hill R.; Majhi P.

首页> 外文期刊>Diffusion and Defect Data. Solid State Data, Part B. Solid State Phenomena >Achieving ultra-shallow junctions in future CMOS devices by a wet processing technique

【24h】

Achieving ultra-shallow junctions in future CMOS devices by a wet processing technique

机译：通过湿法工艺在未来的CMOS器件中实现超浅结

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs and high mobility substrates, including compound semiconductors (III-V). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under low thermal budget environments for III-V materials. Ion implantation into III-V materials presents a problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. This paper presents a potentially defect-free alternative, mono-layer doping (MLD), which utilizes wet processing techniques.

机译：CMOS器件可继续扩展至16nm以下的技术节点，这将有可能通过新架构实现，例如FinFET和包括化合物半导体（III-V）的高迁移率基板。在这些技术节点上，对于III-V材料，在低热预算环境下将需要具有高掺杂剂活化作用的突然沟道掺杂分布。离子注入到III-V材料中会引起问题，因为它会引起晶体损伤，从而可能以难以恢复的方式改变化学计量。残留的损坏会导致更高的结泄漏和更低的掺杂剂活化。本文提出了一种潜在的无缺陷替代方法，即单层掺杂（MLD），它利用了湿法工艺技术。

著录项

来源
《Diffusion and Defect Data. Solid State Data, Part B. Solid State Phenomena》 |2012年第null期|共4页
作者
Barnett J.; Hill R.; Majhi P.;
展开▼
作者单位

展开▼
收录信息
原文格式 PDF
正文语种 eng
中图分类半导体物理学;
关键词
InGaAs; Monolayer doping; Sulfur; Ultra-shallow junctions;

机译：InGaAs;单层掺杂;硫;超浅结;

相似文献

外文文献
中文文献
专利

1. Achieving ultra-shallow junctions in future CMOS devices by a wet processing technique [J] . Barnett J., Hill R., Majhi P. Diffusion and Defect Data. Solid State Data, Part B. Solid State Phenomena . 2012,第Null期

机译：通过湿法工艺在未来的CMOS器件中实现超浅结
2. Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices [J] . Lu C.-Y., Sung J.J. IEEE Transactions on Electron Devices . 1991,第2期

机译：亚微米CMOS器件中自对准TiSi / sub 2 /结形成的工艺限制和器件设计折衷
3. Development of an electroless post-processing technique for depositing gold as electrode material on CMOS devices [J] . L. Berdondini, P.D. van der Wal, N.F. de Rooij, Sensors and Actuators. B, Chemical . 2004,第2a3期

机译：开发用于在CMOS器件上沉积金作为电极材料的化学镀后处理技术
4. Achieving ultra-shallow junctions in future CMOS devices by a wet processing technique [C] . Joel Barnett, Richard Hill, Prashant Majhi International Symposium on Ultra Clean Processing of Semiconductor Surfaces . 2012

机译：通过湿法加工技术实现未来CMOS器件中的超浅线
5. Germanosilicide contacts to ultra-shallow p(+)n junctions of nanoscale CMOS integrated circuits by selective deposition of in-situ doped silicon-germanium alloys. [D] . Liu, Jing. 2003

机译：锗硅化物通过选择性沉积原位掺杂的硅锗合金与纳米级CMOS集成电路的超浅p（+）n结接触。
6. Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices [O] . Yinhua Cui, Jeong Yeul Jeong, Yuan Gao, 2020

机译：CMOS逻辑器件中的Via Plug多级互连的工艺优化
7. Sub-micron Junction Termination for 1200V Class Devices toward CMOS Process Compatibility [O] . Seto Kota, Takaishi Junpei, Imaki Hironori, 2013

机译：面向CMOS工艺兼容性的1200V类器件的亚微米级结终端

Achieving ultra-shallow junctions in future CMOS devices by a wet processing technique

摘要

著录项

相似文献

相关主题

期刊订阅