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The effect of thin film stress levels on CMP polish rates for PETEOS wafers

机译:薄膜应力水平对PETEOS晶圆CMP抛光速率的影响

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Chemical mechanical planarisation (CMP) is presently the process of choice for integrated circuit (IC) manufacturers when polishing inter-level oxide layers on silicon wafers to achieve global planarity. This paper will investigate the relationship between the deposited thin film stress levels and the removal rate across the wafer, which some literature maintains as being strongly linear. Experimental results will attempt to show that rather than it being a linear relationship, it is a relationship of the form: R = a e~(b sigma) Given that this relationship is substantially correct, then knowledge of the constants a and b will enable predictions of polishing rates to be made under various stress and pressure conditions. The relationship was modified by the addition of an asymptotic value for removal rate c, which improved the fit for the experimental data to the expression. From this, it is speculated that in future work, pad wear profiles could be developed through selective conditioning which would accommodate wafer bending so as to achieve a constant polishing rate over the whole wafer.
机译:当抛光硅晶片上的层间氧化物层以实现整体平面性时,化学机械平面化(CMP)是目前集成电路制造商(IC)的首选工艺。本文将研究沉积的薄膜应力水平与整个晶圆的去除率之间的关系,一些文献认为该关系是强线性的。实验结果将试图表明,与其说它是线性关系,不如说是一种关系:R = ae〜(b sigma)鉴于这种关系基本上是正确的,因此知道常数a和b将能够进行预测在各种应力​​和压力条件下的抛光速率。通过增加去除率c的渐近值来修改该关系,从而改善了实验数据对表达式的拟合度。据此推测,在将来的工作中,可以通过选择性调节来形成垫磨损曲线,这种调节可以适应晶片的弯曲,从而在整个晶片上实现恒定的抛光速率。

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