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首页> 外文期刊>Journal of Low Power Electronics >Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells
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Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells

机译：使用单独的晶体管阱研究具有大量输入的静态互补金属氧化物半导体栅极的可行性

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摘要

The so-called body effect as well as internal parasitic capacitances impose strong performance limitations on complementary metal-oxide-semiconductor (CMOS) static logic gates such as decreased speed, increased power consumption and high variation of the pin-to-pin delay along the inputs. The severity of this problem increases with the number of inputs of the gate. Like silicon-on-insulator (SOI) technologies, triple-well technologies make it possible to circumvent the body effect by using independent body terminals for each transistor in a series tree, thus allowing the practical implementation of gates with a larger number of inputs. In this paper the authors study the viability of gates with large number of inputs using both, the traditional and the proposed design styles in a regular bulk-CMOS technology. Electrical simulation results on a set of test gates show remarkable performance improvements in delay and power consumption of independent body gates at the expense of a significant area penalty.
机译：所谓的体效应以及内部寄生电容对互补金属氧化物半导体（CMOS）静态逻辑门施加了强大的性能限制，例如速度降低，功耗增加以及沿引脚的引脚间延迟变化很大。输入。该问题的严重性随着门的输入数量而增加。与绝缘体上硅（SOI）技术一样，三阱技术可以通过对串联树中的每个晶体管使用独立的体端子来规避体效应，从而可以实际实现具有大量输入的门。在本文中，作者使用常规块CMOS技术中的传统设计和建议设计样式研究了具有大量输入的门的可行性。一组测试门的电气仿真结果表明，独立车身门的延迟和功耗显着提高，但以面积损失为代价。

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