Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications

Rohit Dhiman; Rajeevan Chandel

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Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications

机译：超低功耗应用中互补金属氧化物半导体缓冲器驱动的互连负载的亚阈值延迟和功率分析

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In this paper, analytical models for timing analysis of a complementary metal-oxide semiconductor buffer driven resistance-inductance-capacitance interconnect load in sub-threshold regime of operation have been proposed. Closed form expressions are given for estimating the output voltage and propagation delay. Analytical model is also provided for resistive current and power estimation. It is shown that operating transistor in the sub-threshold region leads to an order of saving in power dissipation in comparison to normal strong inversion. Therefore, sub-threshold regime is highly suitable for ultra low power circuit design. The analysis has been carried out for three technology nodes viz. 130 nm, 90 nm and 65 nm. The results are verified using SPICE simulations. A good agreement is found between the analytical and the simulation results.

机译：本文提出了用于亚阈值工作状态下互补金属氧化物半导体缓冲器驱动的电阻-电感-电容互连负载时序分析的分析模型。给出了闭合形式的表达式，用于估计输出电压和传播延迟。还提供了用于电阻电流和功率估计的分析模型。结果表明，与正常的强反相相比，在亚阈值区域中工作的晶体管导致节省功率的顺序。因此，亚阈值范围非常适合于超低功耗电路设计。已经对三个技术节点进行了分析。 130 nm，90 nm和65 nm。使用SPICE仿真对结果进行验证。在分析结果和模拟结果之间找到了很好的一致性。

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《Journal of Low Power Electronics》 |2012年第1期|共8页
作者
Rohit Dhiman; Rajeevan Chandel;
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正文语种 eng
中图分类无线电电子学、电信技术;
关键词
Sub-Threshold; RLC Interconnects; Very Large Scale Integration (VLSI); Buffer; Complementary Metal-Oxide Semiconductor (CMOS); Ultra Low Power Dissipation;

机译：亚阈值;RLC互连;超大规模集成（VLSI）;缓冲器;互补金属氧化物半导体（CMOS）;超低功耗;

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专利

1. Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications [J] . Rohit Dhiman, Rajeevan Chandel Journal of Low Power Electronics . 2012,第1期

机译：超低功耗应用中互补金属氧化物半导体缓冲器驱动的互连负载的亚阈值延迟和功率分析
2. Crosstalk analysis of CMOS buffer driven interconnects for ultra-low power applications [J] . Rohit Dhiman, Rajeevan Chandel Journal of Computational Electronics . 2014,第2期

机译：用于超低功耗应用的CMOS缓冲驱动互连的串扰分析
3. Ultra-low power pass-transistor-logic-based delay line design for sub-threshold applications [J] . R.N. Tadros, N. Dasari, P.A. Beerel Electronics Letters . 2016,第23期

机译：亚阈值应用的基于超低功耗通过晶体管逻辑的延迟线设计
4. A Novel Analytical Model for Analysis of Delay and Crosstalk in Non Linear RLC Interconnects for Ultra Low Power Applications [C] . Ravindra J.V.R., Yagateela Pandurangaiah, Prasad Narasimha UKSim 15th International Conference on Computer Modelling and Simulation . 2013

机译：用于超低功耗应用的非线性RLC互连中的延迟和串扰分析的新型分析模型
5. An ultra low-power 5 Gbps vertical-cavity surface-emitting laser-based optical transmitter for optical interconnect applications and access networks. [D] . Thibodeau, Jean-Philippe. 2005

机译：一种基于超低功耗5 Gbps垂直腔面发射激光器的光发射器，用于光互连应用和接入网络。
6. Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference [O] . El Hafed Boufouss, Laurent A. Francis, Valeriya Kilchytska, 2013

机译：超低功率高温和辐射硬互补金属氧化物半导体（CMOS）绝缘体上硅（SOI）电压基准
7. Exploring CMOS logic families in sub-threshold region for ultra low power applications [O] . Kishore Sanapala, K.S.S.D. Madhuri, Mary Sajin Sanju 2014

机译：探索超低功耗应用的子阈值区域中的CMOS逻辑系列
8. Multi-Threshold Complementary Metal-Oxide Semiconductor (MTCMOS) Bus Circuit and Method for Reducing Bus Power Consumption Via Pulsed Standby Switching. [R] . Deogun, H. S., Nowka, K. J., Rao, R. M. 2004

机译：多阈值互补金属氧化物半导体（mTCmOs）总线电路和通过脉冲待机开关降低总线功耗的方法。

Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications

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