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首页> 外文期刊>Journal of Low Power Electronics >Accurate Logic-Level Current Estimation for Digital CMOS Circuits
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Accurate Logic-Level Current Estimation for Digital CMOS Circuits

机译：数字CMOS电路的准确逻辑级电流估计

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摘要

Nowadays, verification of digital integrated circuit has been shifting more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of precision of current estimations when working at higher levels (logic, RT, architectural levels). To solve this problem it is not only necessary to use good current models for switching activity, it is also necessary to calculate this switching activity with high accuracy. In this paper we present an alternative to estimate current consumption using logic-level simulation. To do that, we use a simple but accurate enough current model to calculate the current consumption for each signal transition, and a delay model that obtains high accuracy when it is used to measure the switching activity (the Degradation Delay Model (DDM)). In the paper we present the current model for the CMOS inverter, the characterization process and the model implementation in the logic simulator HALOTIS that includes the DDM. Results show a high accuracy in the estimation of current curves when compared to HSPICE, and a potentially large improvement over conventional approaches.
机译：如今，数字集成电路的验证已越来越多地从时序和面积领域转移到电流和功率估计上。这种验证的主要问题是，在较高级别（逻辑，RT，体系结构级别）工作时，电流估计的精度不足。为了解决该问题，不仅需要使用良好的电流模型来进行开关动作，而且还需要高精度地计算该开关动作。在本文中，我们提出了一种使用逻辑级仿真来估计电流消耗的替代方法。为此，我们使用一个简单但足够准确的电流模型来计算每个信号转换的电流消耗，并使用一个延迟模型（用于测量开关活动）来获得高精度（退化延迟模型（DDM））。在本文中，我们介绍了CMOS逆变器的当前模型，表征过程以及在包含DDM的逻辑仿真器HALOTIS中的模型实现。结果表明，与HSPICE相比，电流曲线的估计具有很高的准确性，并且与传统方法相比可能会有很大的改进。

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