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首页> 外文期刊>Journal of Low Power Electronics >Characterization of Variation Aware Nanoscale Static Random Access Memory Designs
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Characterization of Variation Aware Nanoscale Static Random Access Memory Designs

机译：变异感知纳米级静态随机存取存储器设计的表征

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Threshold voltage variation due to random dopant fluctuations poses a major challenge to the 6-transistor (6T) SRAM scaling, in nanoscaled technologies. In order to continue to enjoy the benefits of CMOS scaling, various SRAM bitcell topologies were proposed which introduce a tradeoff between performance, stability and cell density. In this paper, the 6T SRAM and the alternative SRAM bitcells are investigated on a commercial CMOS 65 nm design platform and are quantified based on read stability, write stability and the impact of V_(th) and L_(gate) variations on the cell yield. The read SNM of the 8T, and the 10T cells are about 50% higher than the 6T cell. The 10T I and 10T II cells use write assist techniques which boost their write SNMs by 22%. The 10T III SRAM cell has an inherent feedback loop which improves its write SNM by 29.21%. The 8T, 10T I and 10T II cells show a 60% improvement in their mean read SNM values and at least 13% reduction in the standard deviation values in the presence of process variations. These cells pass the yield criterion comfortably with a considerable margin. The results demonstrate the scalability of SRAM cells and indicate that with proper cell topology and read/write assist techniques the scaling window is still open for SRAM in the Nanoscale regime.
机译：在纳米级技术中，由于随机掺杂物波动引起的阈值电压变化对6晶体管（6T）SRAM缩放提出了重大挑战。为了继续享受CMOS缩放的好处，提出了各种SRAM位单元拓扑，这些拓扑在性能，稳定性和单元密度之间进行了权衡。本文在商用CMOS 65 nm设计平台上研究了6T SRAM和替代SRAM位单元，并根据读取稳定性，写入稳定性以及V_（th）和L_（gate）变化对单元产量的影响进行了量化。 8T和10T单元的读取SNM比6T单元高约50％。 10T I和10T II单元使用写辅助技术，可将其写SNM提高22％。 10T III SRAM单元具有固有的反馈环路，可将其写入SNM提升29.21％。在存在过程变化的情况下，8T，10T I和10T II单元的平均读取SNM值提高了60％，标准偏差值至少降低了13％。这些电池以相当大的幅度舒适地通过了屈服准则。结果证明了SRAM单元的可扩展性，并表明通过适当的单元拓扑结构和读/写辅助技术，缩放窗口对于SRAM在纳米尺度下仍然是打开的。

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