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首页> 外文期刊>Journal of Low Power Electronics >An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects
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An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects

机译：VLSI互连中用于延迟和降低功耗的备用缓冲区插入方法

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In VLSI interconnects, buffers are used to restore the signal level affected by the parasitic such as line capacitance, inductance, etc.. However buffers have a certain switching time that contributes to overall signal delay. Further, transitions that occur in interconnects give rise to crosstalk delay. Thus the overall delay in interconnects is due to the combined effect of both buffers and the crosstalk delay. In this work, replacement of buffers with Schmitt trigger is proposed for signal restoration. Since the threshold voltage of Schmitt trigger can be designed to be lower than that of buffer, signal can rise early while a large noise margin of Schmitt trigger helps in reducing the noise glitches due to crosstalk. Simulation results show that the Schmitt trigger approach gives 20% delay reduction as compared to 10.4% in case of buffer.
机译：在VLSI互连中，缓冲区用于恢复受寄生影响的信号电平，例如线路电容，电感等。但是缓冲区具有一定的切换时间，这会导致整体信号延迟。此外，互连中发生的过渡会引起串扰延迟。因此，互连中的总延迟是由于两个缓冲器和串扰延迟的综合影响。在这项工作中，建议用施密特触发器代替缓冲器以恢复信号。由于施密特触发器的阈值电压可以设计为低于缓冲器的阈值电压，因此信号可以提早上升，而施密特触发器的较大噪声容限有助于减少由于串扰引起的噪声干扰。仿真结果表明，施密特触发器方法可将延迟减少20％，而使用缓冲器时则为10.4％。

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