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首页> 外文期刊>Journal of Low Power Electronics >Design Matrix Analysis for Capacitive Interpolation Flash ADC
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Design Matrix Analysis for Capacitive Interpolation Flash ADC

机译：电容内插Flash ADC的设计矩阵分析

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摘要

Flash ADC with interpolation featuring high sampling rate has been widely used in high-speed electronics systems. Unfortunately, practical ADC design is an extremely challenging task that has been largely experience-based and trial-and-error oriented. This paper presents a new quantitative ADC design matrix analysis method for interpolated flash ADCs. The new ADC design matrix establishes a quantitative mapping between key specifications of flash ADC chips and various factors at structures, block circuits, devices and technology levels. It depicts the quantitative influences of design parameters, such as, interpolation factor, number of stages, pre-amplifier bandwidth, loading effects, parasitic transistor capacitance, transistor size and electrical parameters on the overall ADC performance including total bandwidth and sampling speed. This new quantitative design matrix aims to provide a practical design methodology for fast and relatively accurate flash ADC design to achieve reasonable whole-chip ADC optimization with a focus on sampling speed and resolution bit analysis in examples. This ADC design matrix was validated by designs of 4-bit flash ADCs in commercial 0.13 μm and 90 nm CMOS technologies.
机译：具有高采样率插值功能的Flash ADC已广泛用于高速电子系统中。不幸的是，实际的ADC设计是一项极富挑战性的任务，很大程度上是基于经验和试错法的。本文提出了一种用于内插闪存ADC的定量ADC设计矩阵分析新方法。新的ADC设计矩阵在闪存ADC芯片的关键规格与结构，模块电路，器件和技术水平的各种因素之间建立了定量映射。它描述了设计参数的定量影响，例如插值因子，级数，前置放大器带宽，负载效应，寄生晶体管电容，晶体管尺寸和电参数对总体ADC性能（包括总带宽和采样速度）的影响。这个新的定量设计矩阵旨在为快速且相对准确的闪存ADC设计提供一种实用的设计方法，以实现合理的全芯片ADC优化，并着重于示例中的采样速度和分辨率位分析。该ADC设计矩阵通过商用0.13μm和90 nm CMOS技术的4位闪存ADC的设计进行了验证。

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